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![Design and Analysis of High Performance Full Adder Cell]( "Design and Analysis of High Performance Full Adder Cell")
Design and Analysis of High Performance Full Adder Cell32,99 €![New Approach to Low Power Full Adder Cell]( "New Approach to Low Power Full Adder Cell")
New Approach to Low Power Full Adder Cell32,99 €![Analysis of various DCVSL Structures and Implementation of Full Adder]( "Analysis of various DCVSL Structures and Implementation of Full Adder")
Analysis of various DCVSL Structures and Implementation of Full Adder32,99 €![Full Adder using CNFET for Mission Critical Applications]( "Full Adder using CNFET for Mission Critical Applications")
Full Adder using CNFET for Mission Critical Applications40,99 €![Improved Architecture Of 256 Bit CSLA For Reduced Area Applications]( "Improved Architecture Of 256 Bit CSLA For Reduced Area Applications")
Improved Architecture Of 256 Bit CSLA For Reduced Area Applications23,99 €![Cmos design of tree multiplier using low power vlsi and full adder]( "Cmos design of tree multiplier using low power vlsi and full adder")
Cmos design of tree multiplier using low power vlsi and full adder30,99 €![Analysis and Design of a DRAM Cell for Low Leakage]( "Analysis and Design of a DRAM Cell for Low Leakage")
Analysis and Design of a DRAM Cell for Low Leakage32,99 €
As technology scales into the nanometer regime leakage current, active power, delay and area are the important metric for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit full adder cell are proposed for mobile applications and a novel technique has been introduced with improved staggered phase damping technique and also Gated Diffusion Input (GDI) technique for further reduction in the Active power. Leakage power is being estimated when the circuits are connected with a sleep transistor, Further compared to the Base case and Design1 and Design2 and GDI Technique when a circuit is connected to sleep transistor. We introduced a new transistor resizing approach for 1bit full adder cells to determine the optimal sleep transistor size which reduce the leakage power and Area. The simulation results depicts that the proposed design also leads to efficient 1bit full adder cells in terms of standby leakage power, active power. We have performed simulations using Microwind 90nm standard CMOS technology at room temperature with supply voltage of 1V.