Lennart Bamberg, Jan Moritz Joseph, Alberto García-Ortiz

3D Interconnect Architectures for Heterogeneous Technologies

Modeling and Optimization

• Broschiertes Buch

Produktbeschreibung

This book describes the first comprehensive approach to the optimization of interconnect architectures in 3D systems on chips (SoCs), specially addressing the challenges and opportunities arising from heterogeneous integration. Readers learn about the physical implications of using heterogeneous 3D technologies for SoC integration, while also learning to maximize the 3D-technology gains, through a physical-effect-aware architecture design. The book provides a deep theoretical background covering all abstraction-levels needed to research and architect tomorrow's 3D-integrated circuits, an extensive set of optimization methods (for power, performance, area, and yield), as well as an open-source optimization and simulation framework for fast exploration of novel designs.

Produktdetails

• Verlag: Springer / Springer International Publishing / Springer, Berlin
• Artikelnr. des Verlages: 978-3-030-98231-7
• 1st ed. 2022
• Seitenzahl: 424
• Erscheinungstermin: 29. Juni 2023
• Englisch
• Abmessung: 235mm x 155mm x 23mm
• Gewicht: 639g
• ISBN-13: 9783030982317
• ISBN-10: 3030982319
• Artikelnr.: 68158398

Autorenporträt

Lennart Bamberg received the B.Sc., M.Sc., and Ph.D. (Dr.-Ing. ) degree with highest honours ("summa cum laude") in electrical and computer engineering from the University of Bremen, Germany, in 2014, 2016, and 2020, respectively. In 2019, he was a Visiting Research Scholar at the Georgia Institute of Technology, Atlanta (USA). This stay was funded by a scholarship of the German Academic Exchange Service, DAAD, and the German Federal Ministry of Education and Research, BMBF. Afterwards, he was a Technical director at GrAI Matter Labs, where he was in charge of the processor architecture for edge AI. Since 2022, he is System Architect at NXP Semiconductors working on secure-element SoCs for mobile phones and wearables. In parallel, he serves as a guest lecturer at the University of Bremen in electrical engineering since 2020. Lennart Bamberg's research interests include low-power and domain-specific computer architectures for embedded systems. He received best-paper awards atinternational conferences and serves as a reviewer and program-committee member for several international conferences and journals. Jan Moritz Joseph got his B.Sc. in medical engineering in 2011 and his M.Sc. in computer science in 2014 from the Universität zu Lübeck, Germany.  From 2008 to 2014 he was a scholarship holder of the German Merit Foundation (Deutsche Studienstiftung e.V.). Dr. Joseph received his Ph.D. from Otto-von-Guericke Universität Magdeburg, Germany, in 2019. The title of his thesis was "Networks-on-Chip for heterogeneous 3D Systems-on-Chip". His Ph.D. was awarded the highest honours "summa cum laude". In 2020, he received the award for the best PhD thesis from the Faculty of Electrical Engineering and Information Technology at Otto-von-Guericke Universität Magdeburg, Germany. From 2019 to 2020 Dr. Joseph was a visiting researcher at Dr. Krishna's Synergy Lab at Georgia Institute of Technology, Atlanta, GA. His stay was partially funded by a scholarship from the German Academic Exchange Service. He joined Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, in June 2020 as a postdoctoral research fellow in the Chair for Software for Systems on Silicon. His research interest are architectures for NoCs, AI accelerators and neuromorphic computing as well as simulation and 3D integration. Alberto García-Ortiz received the Diploma degree in telecommunication systems from the Polytechnic University of Valencia, Spain, in 1998, and the Ph.D. degree (summa cum laude) from the Department of Electrical Engineering and Information Technology, Institute of Microelectronic Systems, Darmstadt University of Technology, Germany, in 2003.,He worked at NewLogic, Austria, for two years. From 2003 to 2005, he worked as a Senior Hardware Design Engineer at the IBM Deutschland Research and Development, Böblingen. Then, he joined the start-up AnaFocus, Spain, where he was responsible for the design andintegration of AnaFocus' next generation Vision Systems-on-Chip. He is currently a Full Professor for the Chair of Integrated Digital Systems at the University of Bremen. His research interests include low-power design and estimation, communication-centric design, SoC integration, and variations-aware design. Dr. Garcia-Ortiz received the Outstanding Dissertation Award from the European Design and Automation Association, in 2004, and an Innovation Award from IBM, in 2005, for his contributions to leakage estimation; he holds two issued patents for that work. He serves as a reviewer of several conferences, journals, and European projects. Thilo Pionteck received the Diploma degree and the Ph.D. (Dr.-Ing.) degree in electrical engineering from Technische Universität Darmstadt, Germany, in 1999 and 2005, respectively.  In 2008, he was appointed as an Assistant Professor of Integrated Circuits and Systems at the Universität zu Lübeck, Germany. From 2012 to 2014, he wasthe substitute of the Chair of Embedded Systems, Technische Universität Dresden, and the Chair of Computer Engineering, Technische Universität Hamburg, Harburg, Germany. In 2015, he was appointed as a Professor with the Chair of Organic Computing, Universität zu Lübeck, with research focus on adaptive digital systems. Finally, in 2016 he was appointed to the Otto-von-Guericke where he is currently the Chair for Hardware-oriented Technical Computer Science and since 2019 managing director of the Institute for Information Technology and Communications. In his research, he focuses on new architectural concepts for the realization of runtime-adaptive, performance- and energy efficient digital systems. Research interests include the areas of NoCs, 3D SoC, adaptive system designs and dynamic partial reconfiguration of FPGAs.

Inhaltsangabe

Part I Introduction.- 1 Introduction to 3D Technologies.- 1.1 Motivation for Heterogenous 3D ICs.- 1.2 3D Technologies.- 1.3 TSV Capacitances-A Problem Resistant to Scaling.- 1.4 Conclusion.- 2 Interconnect Architectures for 3D Technologies.- 2.1 Interconnect Architectures.- 2.2 Overview of Interconnect Architectures for 3D ICs.- 2.3 Three-dimensional Networks on chips.- 2.4 Conclusion.- Part II 3D Technology Modeling.- 3 Power and Performance Formulas.- 3.1 High-Level Formula for the Power Consumption.- 3.2 High-Level Formula for the Propagation Delay.- 3.3 Matrix Formulations.- 3.4 Evaluation.- 3.5 Conclusion.- 4 Capacitance Estimation.- 4.1 Existing Capacitance Models.- 4.2 Edge and MOS Effects on the TSV Capacitances.- 4.3 TSV Capacitance Model.- 4.4 Evaluation.- 4.5 Conclusion.- Part III System Modeling.- xiii.- xiv Contents.- 5 Application and Simulation Models.- 5.1 Overview of the Modeling Approach.- 5.2 Application Traffic Model.- 5.3 Simulation Model of 3D NoCs.- 5.4 Simulator Interfaces.- 5.5 Conclusion.- 6 Bit-level Statistics.- 6.1 Existing Approaches to Estimate the Bit-Level Statistics for.- Single Data Streams.- 6.2 Data-Stream Multiplexing.- 6.3 Bit-Level Statistics with Data-Stream Multiplexing.- 6.4 Evaluation.- 6.5 Conclusion.- 7 Ratatoskr Framework.- 7.1 Ratatoskr for Practitioners.- 7.2 Implementation.- 7.3 Evaluation.- 7.4 Case Study: Link Power Estimation and Optimization.- 7.5 Conclusion.- Part IV 3D-Interconnect Optimization.- 8 Low-Power Technique for 3D Interconnects.- 8.1 Fundamental Idea.- 8.2 Power-Optimal TSV assignment.- 8.3 Systematic Net-to-TSV Assignments.- 8.4 Combination with Traditional Low-Power Codes.- 8.5 Evaluation.- 8.6 Conclusion.- 9 Low-Power Technique for High-Performance 3D.- Interconnects..- 9.1 Edge-Effect-Aware Crosstalk Classification.- 9.2 Existing Approaches and Their Limitations.- 9.3 Proposed Technique.- 9.4 Extension to a Low-Power3D CAC.- 9.5 Evaluation.- 9.6 Conclusion.- 10 Low-Power Technique for High-Performance 3D.- Interconnects (Misaligned).- 10.1 Temporal-Misalignment Effect on the Crosstalk.- 10.2 Exploiting Misalignment to Improve the Performance.- 10.3 Effect on the TSV Power Consumption.- Contents xv.- 10.4 Evaluation.- 10.5 Conclusion.- 11 Low-Power Technique for Yield-Enhanced 3D Interconnects.- 11.1 Existing TSV Yield-Enhancement Techniques.- 11.2 Preliminaries-Logical Impact of TSV Faults.- 11.3 Fundamental Idea.- 11.4 Formal Problem Description.- 11.5 TSV Redundancy Schemes.- 11.6 Evaluation.- 11.7 Case Study.- 11.8 Conclusion.- Part V NoC Optimization for Heterogeneous 3D Integration.- 12 Heterogeneous Buffering for 3D NoCs251.- 12.1 Buffer Distributions and Depths.- 12.2 Routers with Optimized Buffer Distribution.- 12.3 Routers with Optimized Buffer Depths.- 12.4 Evaluation.- 12.5 Discussion.- 12.6 Conclusion.- 13 Heterogeneous Routing for 3D NoCs.- 13.1 Heterogeneity and Routing.- 13.2 Modeling Heterogeneous Technologies.- 13.3 Modeling Communication.- 13.4 Routing Limitations from Heterogeneity.- 13.5 Heterogeneous Routing Algorithms.- 13.6 Heterogeneous Router Architectures.- 13.7 Low-Power Routing in Heterogeneous 3D ICs.- 13.8 Evaluation.- 13.9 Discussion.- 13.10Conclusion.- 14 Heterogeneous Virtualisation for 3D NoCs.- 14.1 Problem Description.- 14.2 Heterogeneous Microarchitectures Exploiting Traffic Imbalance.- 14.3 Evaluation.- 14.4 Conclusion.- 15 Network Synthesis and SoC Floor Planning.- 15.1 Fundamental Idea.- 15.2 Modelling and Optimization.- 15.3 Mixed-Integer Linear Program.- 15.4 Heuristic Solution.- xvi Contents.- 15.5 Evaluation.- 15.6 Conclusion.- Part VI Finale.- 16 Conclusion.- 16.1 Putting it all together.- 16.2 Impact on Future Work.- A Appendix.- B Pseudo Codes.- C Method to Calculate the Depletion-Region Widths.- D Modeling Logical OR Relations.

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Part I Introduction.- 1 Introduction to 3D Technologies.- 1.1 Motivation for Heterogenous 3D ICs.- 1.2 3D Technologies.- 1.3 TSV Capacitances—A Problem Resistant to Scaling.- 1.4 Conclusion.- 2 Interconnect Architectures for 3D Technologies.- 2.1 Interconnect Architectures.- 2.2 Overview of Interconnect Architectures for 3D ICs.- 2.3 Three-dimensional Networks on chips.- 2.4 Conclusion.- Part II 3D Technology Modeling.- 3 Power and Performance Formulas.- 3.1 High-Level Formula for the Power Consumption.- 3.2 High-Level Formula for the Propagation Delay.- 3.3 Matrix Formulations.- 3.4 Evaluation.- 3.5 Conclusion.- 4 Capacitance Estimation.- 4.1 Existing Capacitance Models.- 4.2 Edge and MOS Effects on the TSV Capacitances.- 4.3 TSV Capacitance Model.- 4.4 Evaluation.- 4.5 Conclusion.- Part III System Modeling.- xiii.- xiv Contents.- 5 Application and Simulation Models.- 5.1 Overview of the Modeling Approach.- 5.2 Application Traffic Model.- 5.3 Simulation Model of 3D NoCs.- 5.4 Simulator Interfaces.- 5.5 Conclusion.- 6 Bit-level Statistics.- 6.1 Existing Approaches to Estimate the Bit-Level Statistics for.- Single Data Streams.- 6.2 Data-Stream Multiplexing.- 6.3 Bit-Level Statistics with Data-Stream Multiplexing.- 6.4 Evaluation.- 6.5 Conclusion.- 7 Ratatoskr Framework.- 7.1 Ratatoskr for Practitioners.- 7.2 Implementation.- 7.3 Evaluation.- 7.4 Case Study: Link Power Estimation and Optimization.- 7.5 Conclusion.- Part IV 3D-Interconnect Optimization.- 8 Low-Power Technique for 3D Interconnects.- 8.1 Fundamental Idea.- 8.2 Power-Optimal TSV assignment.- 8.3 Systematic Net-to-TSV Assignments.- 8.4 Combination with Traditional Low-Power Codes.- 8.5 Evaluation.- 8.6 Conclusion.- 9 Low-Power Technique for High-Performance 3D.- Interconnects..- 9.1 Edge-Effect-Aware Crosstalk Classification.- 9.2 Existing Approaches and Their Limitations.- 9.3 Proposed Technique.- 9.4 Extension to a Low-Power3D CAC.- 9.5 Evaluation.- 9.6 Conclusion.- 10 Low-Power Technique for High-Performance 3D.- Interconnects (Misaligned).- 10.1 Temporal-Misalignment Effect on the Crosstalk.- 10.2 Exploiting Misalignment to Improve the Performance.- 10.3 Effect on the TSV Power Consumption.- Contents xv.- 10.4 Evaluation.- 10.5 Conclusion.- 11 Low-Power Technique for Yield-Enhanced 3D Interconnects.- 11.1 Existing TSV Yield-Enhancement Techniques.- 11.2 Preliminaries—Logical Impact of TSV Faults.- 11.3 Fundamental Idea.- 11.4 Formal Problem Description.- 11.5 TSV Redundancy Schemes.- 11.6 Evaluation.- 11.7 Case Study.- 11.8 Conclusion.- Part V NoC Optimization for Heterogeneous 3D Integration.- 12 Heterogeneous Buffering for 3D NoCs251.- 12.1 Buffer Distributions and Depths.- 12.2 Routers with Optimized Buffer Distribution.- 12.3 Routers with Optimized Buffer Depths.- 12.4 Evaluation.- 12.5 Discussion.- 12.6 Conclusion.- 13 Heterogeneous Routing for 3D NoCs.- 13.1 Heterogeneity and Routing.- 13.2 Modeling Heterogeneous Technologies.- 13.3 Modeling Communication.- 13.4 Routing Limitations from Heterogeneity.- 13.5 Heterogeneous Routing Algorithms.- 13.6 Heterogeneous Router Architectures.- 13.7 Low-Power Routing in Heterogeneous 3D ICs.- 13.8 Evaluation.- 13.9 Discussion.- 13.10Conclusion.- 14 Heterogeneous Virtualisation for 3D NoCs.- 14.1 Problem Description.- 14.2 Heterogeneous Microarchitectures Exploiting Traffic Imbalance.- 14.3 Evaluation.- 14.4 Conclusion.- 15 Network Synthesis and SoC Floor Planning.- 15.1 Fundamental Idea.- 15.2 Modelling and Optimization.- 15.3 Mixed-Integer Linear Program.- 15.4 Heuristic Solution.- xvi Contents.- 15.5 Evaluation.- 15.6 Conclusion.- Part VI Finale.- 16 Conclusion.- 16.1 Putting it all together.- 16.2 Impact on Future Work.- A Appendix.- B Pseudo Codes.- C Method to Calculate the Depletion-Region Widths.- D Modeling Logical OR Relations.