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- With the advent of deep sub-micron technology, System-on-Chip (SOC) architectures are becoming possible for a range of applications. However, as single chip systems become a reality, ingenious solutions are needed for many arising architectural issues. One such issue is the design of an on-chip interconnect to facilitate communications among different IP blocks. - The integration of multiple cores on a single die has signaled the beginning of a communication- centric design philosophy rather than a computationally centered one. Further, the introduction of nano-scale technology has…mehr

Produktbeschreibung
- With the advent of deep sub-micron technology, System-on-Chip (SOC) architectures are becoming possible for a range of applications. However, as single chip systems become a reality, ingenious solutions are needed for many arising architectural issues. One such issue is the design of an on-chip interconnect to facilitate communications among different IP blocks. - The integration of multiple cores on a single die has signaled the beginning of a communication- centric design philosophy rather than a computationally centered one. Further, the introduction of nano-scale technology has emphasized the importance of a communication-conscious design where global wiring delays do not scale down as fast as gate delays in newer technologies. Therefore, on- chip interconnections are expected to be a major hurdle in the design of embedded SoC architectures and high-performance multicore architectures alike.
Autorenporträt
Jongman Kim is an assistant professor in the School of Electrical and Computer Engineering, Georgia Institute of Technology. Dr. Kim received his Ph.D. degree in Computer Science and Engineering from The Pennsylvania State University in 2007.