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In order to enhance the performance of a computer,
most modern processors use superscalar architecture
and raise the clock frequency. Superscalar
architecture can execute more than one instruction
per each cycle. The amount of instruction level
parallelism will become more and more important when
superscalar issue is increased. In some schemes [6,
14], instructions can be speculatively waked up. The
more instructions are waked up, the more ILP is
exploited, hence IPC is increased. We can adopt the
speculative aspect to wakeup more instructions. But
the ILP is still limited by the true data dependency.
In this paper proposed the speculative wakeup logic
with value prediction mechanism to overcome the data
dependency that will exploit instruction level
parallelism. And in order to reduce the recovery
frequency, we also propose the priority base select
logic with two bit counter. In our experiment, our
model will enhance 18.02% performance.
most modern processors use superscalar architecture
and raise the clock frequency. Superscalar
architecture can execute more than one instruction
per each cycle. The amount of instruction level
parallelism will become more and more important when
superscalar issue is increased. In some schemes [6,
14], instructions can be speculatively waked up. The
more instructions are waked up, the more ILP is
exploited, hence IPC is increased. We can adopt the
speculative aspect to wakeup more instructions. But
the ILP is still limited by the true data dependency.
In this paper proposed the speculative wakeup logic
with value prediction mechanism to overcome the data
dependency that will exploit instruction level
parallelism. And in order to reduce the recovery
frequency, we also propose the priority base select
logic with two bit counter. In our experiment, our
model will enhance 18.02% performance.