Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul

A Pipelined Multi-Core Machine with Operating System Support

Hardware Implementation and Correctness Proof

• Broschiertes Buch

Produktbeschreibung

This work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.

It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:

- MIPS instruction set architecture (ISA) for application and for system programming

- cache coherent memory system

- store buffers in front of the data caches

- interrupts and exceptions
- memory management units (MMUs)

- pipelined processors: the classical five-stage pipeline is extended by two pipeline

stages for address translation

- local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)

- I/O-interrupt controller and a disk

Produktdetails

• Theoretical Computer Science and General Issues 9999
• Verlag: Springer / Springer International Publishing / Springer, Berlin
• Artikelnr. des Verlages: 978-3-030-43242-3
• 1st ed. 2020
• Seitenzahl: 644
• Erscheinungstermin: 10. Mai 2020
• Englisch
• Abmessung: 235mm x 155mm x 35mm
• Gewicht: 961g
• ISBN-13: 9783030432423
• ISBN-10: 3030432424
• Artikelnr.: 58662159

Inhaltsangabe

Introductory material.- on hierarchical hardware design.- hardware library.- basic processor design.- pipelining.- cache memory systems.- interrupt mechanism.- self modification, instruction buffer and nondeterministic ISA.- memory management units.- store buffers.- multi-core processors.- advanced programmable interrupt controllers (APICs).- adding a disk.- I/O apic.