The book addresses the fundamental physics behind the operation of various FETs, as well as challenges and solutions with the FETs for the device to circuit level design and simulation. This book will provide an overview of new semiconductor devices and their applicability in electronic circuit design.
The book addresses the fundamental physics behind the operation of various FETs, as well as challenges and solutions with the FETs for the device to circuit level design and simulation. This book will provide an overview of new semiconductor devices and their applicability in electronic circuit design.
Dharmendra Singh Yadav received the Ph.D. degree in electronics and communication engineering from the PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, India. He is currently working as Assistant Professor (Grade-I) in National Institute of Technology (NIT), Kurukshetra, Haryana India. He has more than 60 international repute publications and 4 book chapters. His current research interest includes VLSI Design: Nano-electronics Devices, Thin films transistors, Semiconductor Device, Negative Capacitance, Nanosheet FETS and circuits. Device Modeling: MOS Devices Modeling and Numerical simulation analysis of Semiconductor devices Electrical Characterization of semiconductor devices in MHz and THz frequency ranges. Circuit Design: Ultra Low Power SRAM / DRAM / RRAM based Memory Circuit Design from Devices to Array Architecture using CMOS and Advanced CMOS Devices technologies. Machine Learning in Semiconductor device/circuit-based application in research. Sukeshni Tirkey received the Ph.D. degree in electronics and communication engineering from the PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, India. She is currently working in Maulana Azad National Institute of Technology (MANIT), Bhopal, Madhya Pradesh India. She has more than 20 international publications in reputed journals/conferences. Her current research interest includes VLSI Design: Nano-electronics Devices, Thin films transistors, Semiconductor Device, Negative Capacitance, Nanosheet FETS and circuits. Shiromani Balmukund Rahi received his Ph D from the Indian Institute of Technology Kanpur, Uttar Pradesh, and did his postdoctoral research work at the Electronics Department, University Mostefa Benboulaid of Batna, Algeria and Korea Military Academy Seoul, Republic of Korea. He is working at University School of Information and Communication Technology Gautam Buddha University Greater Noida, Uttar Pradesh, India. He has published 25 journal articles, 18 book chapters and 2 proceedings. He has edited and successfully published 7 books. He is also associated for advanced research work at the Indian Institute of Technology Kanpur and the Electronics Department of the University Mostefa Benboulaid for the development of ultra-low-power devices such as TFETs, negative-capacitance (NC) TFETs, and nanosheet FETs.
Inhaltsangabe
1. Future Prospective beyond CMOS Technology: From Silicon-based devices to alternate devices. 2. Design and Challenges in Tunnel FET. 3. Modelling Approaches to Field Effect Transistor. 4. Dynamics of Trap States in Organic Thin-Film Transistors (OTFT's). 5. An Insightful Study and Investigation of Tunnel FET and its Application in the Biosensing Domain. 6. Optimization of Hetero buried Oxide Pocket doped Gate engineered Tunnel FET structure. 7. Comprehensive Analysis of NC-L-TFET. 8. Thermal Behavior of Si-doped MoS2 based Step Structure DG-TFET. 9. Implementation of Logic gates using Step-Channel TFET. 10. CMOS-based SRAM with Odd Transistors Configuration: An Extensive Study. 11. Gate-All-Around Nanosheet FET device simulation methodology using Sentaurus TCAD. 12. Device Simulation process on TCAD
1. Future Prospective beyond CMOS Technology: From Silicon-based devices to alternate devices. 2. Design and Challenges in Tunnel FET. 3. Modelling Approaches to Field Effect Transistor. 4. Dynamics of Trap States in Organic Thin-Film Transistors (OTFT's). 5. An Insightful Study and Investigation of Tunnel FET and its Application in the Biosensing Domain. 6. Optimization of Hetero buried Oxide Pocket doped Gate engineered Tunnel FET structure. 7. Comprehensive Analysis of NC-L-TFET. 8. Thermal Behavior of Si-doped MoS2 based Step Structure DG-TFET. 9. Implementation of Logic gates using Step-Channel TFET. 10. CMOS-based SRAM with Odd Transistors Configuration: An Extensive Study. 11. Gate-All-Around Nanosheet FET device simulation methodology using Sentaurus TCAD. 12. Device Simulation process on TCAD
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