This book characterizes the HEMT based on InAs III-V material to achieve outstanding current and frequency performance. It explains different types of device architectures available to enhance the performance including InAs based single gate (SG) HEMT and double gate (DG) HEMT. The noise analysis of InAs based SG and DG-HEMT is also discussed.
This book characterizes the HEMT based on InAs III-V material to achieve outstanding current and frequency performance. It explains different types of device architectures available to enhance the performance including InAs based single gate (SG) HEMT and double gate (DG) HEMT. The noise analysis of InAs based SG and DG-HEMT is also discussed.Hinweis: Dieser Artikel kann nur an eine deutsche Lieferadresse ausgeliefert werden.
Dr. N. Mohankumar was born in India in 1978. He received his B.E. Degree from Bharathiyar University, Tamilnadu, India, in 2000 and M.E. & Ph.D Degree from Jadavpur University, Kolkata in 2004 & 2010. He joined the Nano Device Simulation Laboratory in 2007 and worked as a Senior Research Fellow under CSIR direct Scheme till September 2009. Later he joined SKP Engineering College as a Professor to develop research activities in VLSI and NANO technology. He initiated and formed the centre of excellence in VLSI and NANO technology at SKP Engg college at the cost of 1 crore. MoU was signed between SKP and Tokyo Institute of technology, Japan and New Jersey Institute of technology under his guidance. In the year 2010 he visited Tokyo institute of technology, Japan as a visiting professor for the period of three months. In the year 2012 he visited New Jersy Institute of Technology, USA as a visiting professor for a period of 2 months. In 2013 he visited National Chaio Tung University Taiwan as a Research Professor for 2 Weeks. He is currently working as a Professor & Head of EECE Department at GITAM Deemed to be University, Bengaluru Campus. He is a Senior Member of IEEE and served as Secretary of IEEE, EDS Calcutta chapter from 2007 to 2010. He served as a Chairman of IEEE EDS Madras Chapter from (2010 - 2017). He has about 70 International journal publications in reputed journals and about 50 international conference proceedings. He received the carrier award for young teachers (CAYT) from AICTE , New Delhi, in 2012-2014. He is a recognized supervisor for research under Anna University and Jadavpur University. 15 PhD Scholars have completed under his supervision. More than 50 M.E students have done their thesis under his guidance. At present, he is guiding 3 PhD Research scholars and 2 M.E students. His research interest includes modeling and simulation study of HEMTs, optimization of devices for RF applications and characterization of advanced HEMT architecture, Terahertz Electronics, High Frequency Imaging, Sensors and Communication.
Inhaltsangabe
1. Introduction to III-V materials and HEMT Structure. 2. III-V Hetero Structure Devices for Ultra Low, High Power and High Breakdown Applications. 3. III-V Hetero Structure Devices for High Frequency Applications. 4. Overview of THz Applications. 5. Device and Simulation Framework of InAs HEMTs. 6. Single Gate (SG)InAs Based HEMTs Architecture for THz Applications. 7. Effect of Gate Scaling and Composite Channel in InAsHEMT. 8. Double Gate (DG) InAs Based HEMT Architecture for THz Applications. 9. Influence of Dual Channel and Drain Side Recess Length in Double Gate InAs HEMTs. 10. Noise Analysis in Dual Quantum Well InAs Based Double Gate (DG) - HEMT
1. Introduction to III-V materials and HEMT Structure. 2. III-V Hetero Structure Devices for Ultra Low, High Power and High Breakdown Applications. 3. III-V Hetero Structure Devices for High Frequency Applications. 4. Overview of THz Applications. 5. Device and Simulation Framework of InAs HEMTs. 6. Single Gate (SG)InAs Based HEMTs Architecture for THz Applications. 7. Effect of Gate Scaling and Composite Channel in InAsHEMT. 8. Double Gate (DG) InAs Based HEMT Architecture for THz Applications. 9. Influence of Dual Channel and Drain Side Recess Length in Double Gate InAs HEMTs. 10. Noise Analysis in Dual Quantum Well InAs Based Double Gate (DG) - HEMT
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