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Advances in Computer Systems Architecture 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings

Aus der Reihe Lecture Notes in Computer Science

49,99 €

inkl. gesetzl. MwSt., Versandkostenfrei

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

30.07.2007

Abbildungen

XIII, 402 p.

Herausgeber

Lynn Choi + weitere

Verlag

Springer Berlin

Seitenzahl

402

Maße (L/B/H)

23,5/15,5/2,3 cm

Gewicht

628 g

Auflage

2007

Sprache

Englisch

ISBN

978-3-540-74308-8

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

30.07.2007

Abbildungen

XIII, 402 p.

Herausgeber

Verlag

Springer Berlin

Seitenzahl

402

Maße (L/B/H)

23,5/15,5/2,3 cm

Gewicht

628 g

Auflage

2007

Sprache

Englisch

ISBN

978-3-540-74308-8

Herstelleradresse

Springer-Verlag KG
Sachsenplatz 4-6
1201 Wien
AT

Email: ProductSafety@springernature.com

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  • Produktbild: Advances in Computer Systems Architecture
  • Produktbild: Advances in Computer Systems Architecture
  • A Compiler Framework for Supporting Speculative Multicore Processors.- Power-Efficient Heterogeneous Multicore Technology for Digital Convergence.- StarDBT: An Efficient Multi-platform Dynamic Binary Translation System.- Unbiased Branches: An Open Problem.- An Online Profile Guided Optimization Approach for Speculative Parallel Threading.- Entropy-Based Profile Characterization and Classification for Automatic Profile Management.- Laplace Transformation on the FT64 Stream Processor.- Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation.- Evolution of NAND Flash Memory Interface.- FCC-SDP: A Fast Close-Coupled Shared Data Pool for Multi-core DSPs.- Exploiting Single-Usage for Effective Memory Management.- An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories.- An Effective Design of Master-Slave Operating System Architecture for Multiprocessor Embedded Systems.- Optimal Placement of Frequently Accessed IPs in Mesh NoCs.- An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips.- Performance of Keyword Connection Algorithm in Nested Mobility Networks.- Leakage Energy Reduction in Cache Memory by Software Self-invalidation.- Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters.- Runtime Performance Projection Model for Dynamic Power Management.- A Power-Aware Alternative for the Perceptron Branch Predictor.- Power Consumption and Performance Analysis of 3D NoCs.- A Design Methodology for Performance-Resource Optimization of a Generalized 2D Convolution Architecture with Quadrant Symmetric Kernels.- Bipartition Architecture for Low Power JPEG Huffman Decoder.- A SWP Specification for Sequential Image Processing Algorithms.- A Stream System-on-ChipArchitecture for High Speed Target Recognition Based on Biologic Vision.- FPGA-Accelerated Active Shape Model for Real-Time People Tracking.- Performance Evaluation of Evolutionary Multi-core and Aggressively Multi-threaded Processor Architectures.- Synchronization Mechanisms on Modern Multi-core Architectures.- Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs.- Generalized Wormhole Switching: A New Fault-Tolerant Mathematical Model for Adaptively Wormhole-Routed Interconnect Networks.- Open Issues in MPI Implementation.- Implicit Transactional Memory in Kilo-Instruction Multiprocessors.- Design of a Low–Power Embedded Processor Architecture Using Asynchronous Function Units.- A Bypass Mechanism to Enhance Branch Predictor for SMT Processors.- Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor.- Architectural Solution to Object-Oriented Programming.