Andere Kunden interessierten sich auch für
![Current Mode Signalling for on Chip Interconnect]( "Current Mode Signalling for on Chip Interconnect")
Current Mode Signalling for on Chip Interconnect23,99 €![FPGA Implementation of Adaptive Digital Filter for Medical Application]( "FPGA Implementation of Adaptive Digital Filter for Medical Application")
FPGA Implementation of Adaptive Digital Filter for Medical Application23,99 €![Digital Image Watermarking: Implementation On FPGA & Programmable SoC]( "Digital Image Watermarking: Implementation On FPGA & Programmable SoC")
Digital Image Watermarking: Implementation On FPGA & Programmable SoC53,99 €![Run-Time Customisation of Soft-Core CPUs on FPGA]( "Run-Time Customisation of Soft-Core CPUs on FPGA")
Run-Time Customisation of Soft-Core CPUs on FPGA32,99 €![Speed Control of Synchronous Motor using FPGA]( "Speed Control of Synchronous Motor using FPGA")
Speed Control of Synchronous Motor using FPGA32,99 €![Fractional FPGA Neural Networks]( "Fractional FPGA Neural Networks")
Fractional FPGA Neural Networks32,99 €![Hand Book on Hardware Cryptography - Algorithms and Analysis]( "Hand Book on Hardware Cryptography - Algorithms and Analysis")
Hand Book on Hardware Cryptography - Algorithms and Analysis45,99 €
Images/Videos are being used in various kinds of applications as the source of information like outdoor surveillance. Some cameras are not able to perform well in different conditions e.g. low, complex and nonlinear lighting conditions. There is a need of high performance video enhancement system that can fulfill the severe system requirements. We proposed the FPGA (Field Programmable Gate Array) architecture in which input frame is inverted and ALE (Air Light Estimation) and TE (Transmission Estimation) is formed on this inverted frame. After ALE and TE enhanced frame is obtained and then inverted again. The architecture is synthesized on Virtex-6 family of FPGA (XC6VLX75T FF884). The architecture meets real time to compute 200 Mpixels/sec and architecture can enhance 640x480 resolution frame in 172.65 µs. The Proposed architecture cops with multiple level-dependent computations by using pipelining that can achieve the high throughput which is favorable for real time applications