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A compact MOSFET I-V model for estimating the drain current of sub-90nm MOSFET in the linear and saturation regions is proposed. It is a modification of nth-power law model introduced by Sakurai and Newton. The proposed model provides more accurate relationship between the channel length modulation and gate voltage in the saturation region. New parameters are introduced for better characterization of drain current of MOSFET at lower VGS and VDS. The proposed model is compared with Modified Sakurai-Newton (MSN) Current model and Extended-Sakurai-Newton (ESN) Compact MOSFET model, and it is found that the proposed model is much more accurate. The model provides precise estimation of drain current as well as the delay of a CMOS inverter. The drain characteristics predicted by the proposed model match with BSIM4v7 simulation with an average error of 1.33% and the delay estimations of CMOS inverter have an average error of 0.03 %( 0.12% maximum) in 90nm process technology.