This book guides readers through the design of hardware architectures using VHDL for digital communication and image processing applications that require performance computing. Further it includes the description of all the VHDL-related notions, such as language, levels of abstraction, combinational vs. sequential logic, structural and behavioral description, digital circuit design, and finite state machines. It also includes numerous examples to make the concepts presented in text more easily understandable.
This book guides readers through the design of hardware architectures using VHDL for digital communication and image processing applications that require performance computing. Further it includes the description of all the VHDL-related notions, such as language, levels of abstraction, combinational vs. sequential logic, structural and behavioral description, digital circuit design, and finite state machines. It also includes numerous examples to make the concepts presented in text more easily understandable.
Bogdan Belean was born in Tirgu-Mures, Romania, on February 7, 1983. He received the B.E. and Ph.D. degrees in electronics and telecommunication engineering from the Technical University of Cluj-Napoca, Romania in 2006 and 2010, respectively. Since 2008, he is involved in didactic activates as a research assistant and later as a Lecturer within the Technical University of Cluj-Napoca, Department of Communications. In 2011, Dr. Belean joined the department of Applied Physics within the National Institute for R&D of Isotopic and Molecular Technology, Cluj-Napoca. His research interests include signal and image processing, bioinformatics and application specific hardware architectures for parallel computing. His research results include over 30 publications and two open-source software solutions for bio-medical image analysis.
Inhaltsangabe
Introduction to VHDL.- High Throughput Hardware Architecture for LDPC decoders.- Hardware Architecture for Hamming Codes.- Hardware Architecture for Edge Detection.- Hardware architectures for iterative algorithm implementations.- Content addressable memories (CAM) for search algorithms optimization.
Introduction to VHDL.- High Throughput Hardware Architecture for LDPC decoders.- Hardware Architecture for Hamming Codes.- Hardware Architecture for Edge Detection.- Hardware architectures for iterative algorithm implementations.- Content addressable memories (CAM) for search algorithms optimization.
Introduction to VHDL.- High Throughput Hardware Architecture for LDPC decoders.- Hardware Architecture for Hamming Codes.- Hardware Architecture for Edge Detection.- Hardware architectures for iterative algorithm implementations.- Content addressable memories (CAM) for search algorithms optimization.
Introduction to VHDL.- High Throughput Hardware Architecture for LDPC decoders.- Hardware Architecture for Hamming Codes.- Hardware Architecture for Edge Detection.- Hardware architectures for iterative algorithm implementations.- Content addressable memories (CAM) for search algorithms optimization.
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