Andere Kunden interessierten sich auch für
![Processor Design]( "Processor Design")
Processor Design116,99 €![Design of Energy-Efficient Application-Specific Instruction Set Processors]( "Design of Energy-Efficient Application-Specific Instruction Set Processors")
Design of Energy-Efficient Application-Specific Instruction Set Processors119,99 €![Design of Energy-Efficient Application-Specific Instruction Set Processors]( "Design of Energy-Efficient Application-Specific Instruction Set Processors")
Design of Energy-Efficient Application-Specific Instruction Set Processors77,99 €![Processor Design]( "Processor Design")
Processor Design110,99 €![Digital Baseband Processor for 802.11a in a Reconfigurable Environment]( "Digital Baseband Processor for 802.11a in a Reconfigurable Environment")
Digital Baseband Processor for 802.11a in a Reconfigurable Environment32,99 €![ASIC Design for a Coherent Optical Receiver DSPU]( "ASIC Design for a Coherent Optical Receiver DSPU")
ASIC Design for a Coherent Optical Receiver DSPU32,99 €![Interface IC Design for MEMS Resonant Devices]( "Interface IC Design for MEMS Resonant Devices")
Interface IC Design for MEMS Resonant Devices44,99 €
OpenSPARC T1 is the first open-source, multi-threaded and multi-cored processor developed by SUN micro-systems. The objective of this book is to carry out an ASIC design of the core of this processor using the 130nm CMOS technology. Starting from the open-source RTL description of the OpenSPARC T1 processor core, several modifications like memory mapping, reducing the processor threads and suppressing the test pins were made in order to reduce the processor size to fir it into a 4 x 4 mm2 die area as required by the technology supplier. The correct functionality of the modified RTL description of this processor was verified against over 500 test scripts given by SUN Inc. Next, to convert the design from the RTL form to its gate level equivalent the design was synthesized. Subsequently, the design was physically implemented using the Place and Route flow, including the normal steps like floorplanning, placement, optimization, clock tree synthesis (CTS) and routing. Finally, the design was verified by a series of verification and performance evaluation tests to guarantee its functionality and performance.