This book presents state-of-the-art research results from leading electronic design automation (EDA) researchers on automated approaches for generating cyber-secure, smart hardware. The authors first provide brief background on high-level synthesis principles and motivate the need for secure design during behavioral synthesis. Then they provide readers with synthesis techniques for six automated security solutions, namely, hardware obfuscation, hardware Trojan detection, IP watermarking, state encoding, side channel attack resistance, and information flow tracking. Provides a single-source…mehr
This book presents state-of-the-art research results from leading electronic design automation (EDA) researchers on automated approaches for generating cyber-secure, smart hardware. The authors first provide brief background on high-level synthesis principles and motivate the need for secure design during behavioral synthesis. Then they provide readers with synthesis techniques for six automated security solutions, namely, hardware obfuscation, hardware Trojan detection, IP watermarking, state encoding, side channel attack resistance, and information flow tracking. Provides a single-source reference to behavioral synthesis for hardware security;Describes automatic synthesis techniques for algorithmic obfuscation, using code transformations;Includes behavioral synthesis techniques for intellectual property protection.
Srinivas Katkoori is an Associate Professor of Computer Science and Engineering at the University of South Florida, Florida, Tampa, FL, USA. His research interests include VLSI design and CAD, high-level synthesis, low power VLSI synthesis, IC reliability, evolutionary algorithms, and hardware security. He has authored over 100 peer-reviewed journal and conference papers. He holds one U.S. patent (6 963 217). He was a recipient of the 2001 NSF Career Award, the 2002¿2003 USF Outstanding Faculty Research Achievement Award, the 2005 Outstanding Engineering Educator Award from the IEEE Florida Council (Region 3), the 2007¿2008 USF Undergraduate Teaching Award, and the 2013 USF Jerome Krivanek Distinguished Teacher Award. Dr. Katkoori received the Ph.D. degree from the University of Cincinnati, Cincinnati, OH, USA, in 1998. Dr. Katkoori is a Senior Member of ACM and IEEE. Sheikh Ariful Islam received the B.Sc. degree in Electronics and Communication Engineering from Khulna University of Engineering and Technology, Bangladesh, in 2011. He is currently pursuing Ph.D. degree in Computer Engineering at the University of South Florida, Tampa. His current research interests include the development of security and reliability aware high-level synthesis tools. To date, he has published 7 papers in peer-reviewed conferences and journals. He received best paper nomination at 2018 AsianHOST Conference held in Hong Kong. Before he joined USF, he served as lecturer in Bangladesh for two years. He has extensive teaching experience in computer architecture and system design. He completed an internship at ON Semiconductor in Fall 2018.
Inhaltsangabe
Introduction.- Background.- Techniques for algorithm-level obfuscation during high-level synthesis.- High-level synthesis of key based obfuscated RTL datapaths.- RTL Hardware IP protection Using Key-Based Control and Data Flow Obfuscation.- Empirical Word-Level Analysis of Arithmetic Module Architectures for Hardware Trojan Susceptibility.- Behavioral synthesis techniques for intellectual property protection.- Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis.- High-Level Synthesis for Side-Channel Defense.- On state encoding against power analysis attacks for finite state controllers.- Examining the consequences of high-level synthesis optimizations on power side-channel.- Towards a timing attack aware high-level synthesis of integrated circuits.- High-Level Synthesis with Timing-Sensitive Information Flow Enforcement.- Mitigating information leakage during critical communication using S*FSM.- Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPsThrough Security-Driven Task Scheduling.- Securing industrial control system with high level synthesis.- Conclusions and open research problems.
Introduction.- Background.- Techniques for algorithm-level obfuscation during high-level synthesis.- High-level synthesis of key based obfuscated RTL datapaths.- RTL Hardware IP protection Using Key-Based Control and Data Flow Obfuscation.- Empirical Word-Level Analysis of Arithmetic Module Architectures for Hardware Trojan Susceptibility.- Behavioral synthesis techniques for intellectual property protection.- Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis.- High-Level Synthesis for Side-Channel Defense.- On state encoding against power analysis attacks for finite state controllers.- Examining the consequences of high-level synthesis optimizations on power side-channel.- Towards a timing attack aware high-level synthesis of integrated circuits.- High-Level Synthesis with Timing-Sensitive Information Flow Enforcement.- Mitigating information leakage during critical communication using S*FSM.- Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPsThrough Security-Driven Task Scheduling.- Securing industrial control system with high level synthesis.- Conclusions and open research problems.
Introduction.- Background.- Techniques for algorithm-level obfuscation during high-level synthesis.- High-level synthesis of key based obfuscated RTL datapaths.- RTL Hardware IP protection Using Key-Based Control and Data Flow Obfuscation.- Empirical Word-Level Analysis of Arithmetic Module Architectures for Hardware Trojan Susceptibility.- Behavioral synthesis techniques for intellectual property protection.- Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis.- High-Level Synthesis for Side-Channel Defense.- On state encoding against power analysis attacks for finite state controllers.- Examining the consequences of high-level synthesis optimizations on power side-channel.- Towards a timing attack aware high-level synthesis of integrated circuits.- High-Level Synthesis with Timing-Sensitive Information Flow Enforcement.- Mitigating information leakage during critical communication using S*FSM.- Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPsThrough Security-Driven Task Scheduling.- Securing industrial control system with high level synthesis.- Conclusions and open research problems.
Introduction.- Background.- Techniques for algorithm-level obfuscation during high-level synthesis.- High-level synthesis of key based obfuscated RTL datapaths.- RTL Hardware IP protection Using Key-Based Control and Data Flow Obfuscation.- Empirical Word-Level Analysis of Arithmetic Module Architectures for Hardware Trojan Susceptibility.- Behavioral synthesis techniques for intellectual property protection.- Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis.- High-Level Synthesis for Side-Channel Defense.- On state encoding against power analysis attacks for finite state controllers.- Examining the consequences of high-level synthesis optimizations on power side-channel.- Towards a timing attack aware high-level synthesis of integrated circuits.- High-Level Synthesis with Timing-Sensitive Information Flow Enforcement.- Mitigating information leakage during critical communication using S*FSM.- Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPsThrough Security-Driven Task Scheduling.- Securing industrial control system with high level synthesis.- Conclusions and open research problems.
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