Andere Kunden interessierten sich auch für
![Vlsi: Integrated Systems on Silicon]( "Vlsi: Integrated Systems on Silicon")
Vlsi: Integrated Systems on Silicon430,99 €![VLSI: Integrated Systems on Silicon]( "VLSI: Integrated Systems on Silicon")
VLSI: Integrated Systems on Silicon256,99 €![Synthesis of Embedded Software]( "Synthesis of Embedded Software")
Synthesis of Embedded Software74,99 €![Precision Assembly Technologies for Mini and Micro Products]( "Precision Assembly Technologies for Mini and Micro Products")
Precision Assembly Technologies for Mini and Micro Products123,99 €![Interconnect-Centric Design for Advanced Soc and Noc]( "Interconnect-Centric Design for Advanced Soc and Noc")
Interconnect-Centric Design for Advanced Soc and Noc192,99 €![Software Automatic Tuning]( "Software Automatic Tuning")
Software Automatic Tuning110,99 €![Secure Integrated Circuits and Systems]( "Secure Integrated Circuits and Systems")
Secure Integrated Circuits and Systems74,99 €
C Compilers for ASIPs: Automatic Compiler Generation with LISA
by:
Manuel Hohenauer
Rainer Leupers
The ever increasing complexity and performance requirements of modern electronic devices are changing the way embedded systems are designed and implemented today. The current trend is towards programmable System-on-Chip platforms which employ an increasing number of Application Specific Instruction-set Processors (ASIPs) as building blocks. ASIP design platforms comprise retargetable software development tools that can be adapted quickly to varying target processor configurations. Such tools are usually driven by a processor model given in an Architecture Description Language (ADL), such as LISA. One of the major challenges in this context is retargetable compilation for high-level programming languages like C. First of all, an ADL must capture the architectural information needed for the tool generation in an unambiguous andconsistent way. This is particularly difficult for compiler and instruction-set simulator. Moreover, there exists a trade-off between the compiler's flexibility and the quality of compiled code.
This book presents a novel approach for ADL-based instruction-set description in order to enable the automatic retargeting of the complete software toolkit from a single ADL processor model. Additionally, this book includes retargetable optimization techniques for architectures with SIMD and Predicated Execution support. Both allows a high speedup in compiler generation and combines high flexibility with acceptable code quality at the same time. Coverage includes a comprehensive overview of retargetable compilers and ADL based processor design, a methodology and related toolkit to generate a C-compiler fully automatically from an ADL processor model, and retargetable code optimization techniques.
Presents a strong background and various perspectives of architecture description language (ADL)-based processor design and the retargetable compilation problem;
Provides the history of ADL based processor design, making the reader knowledgeable about the past research as well as the difficulties faced over time;
Offers an ADL based modelling formalism and corresponding implementation methods, which can be used for automatic compiler retargeting to quickly obtain compiler support for newly developed ASIPs;
Presents retargetable optimization techniques for common ASIP features, which can be quickly adapted to varying target processor configurations and help to meet the stringent performance requirements of embedded applications.
by:
Manuel Hohenauer
Rainer Leupers
The ever increasing complexity and performance requirements of modern electronic devices are changing the way embedded systems are designed and implemented today. The current trend is towards programmable System-on-Chip platforms which employ an increasing number of Application Specific Instruction-set Processors (ASIPs) as building blocks. ASIP design platforms comprise retargetable software development tools that can be adapted quickly to varying target processor configurations. Such tools are usually driven by a processor model given in an Architecture Description Language (ADL), such as LISA. One of the major challenges in this context is retargetable compilation for high-level programming languages like C. First of all, an ADL must capture the architectural information needed for the tool generation in an unambiguous andconsistent way. This is particularly difficult for compiler and instruction-set simulator. Moreover, there exists a trade-off between the compiler's flexibility and the quality of compiled code.
This book presents a novel approach for ADL-based instruction-set description in order to enable the automatic retargeting of the complete software toolkit from a single ADL processor model. Additionally, this book includes retargetable optimization techniques for architectures with SIMD and Predicated Execution support. Both allows a high speedup in compiler generation and combines high flexibility with acceptable code quality at the same time. Coverage includes a comprehensive overview of retargetable compilers and ADL based processor design, a methodology and related toolkit to generate a C-compiler fully automatically from an ADL processor model, and retargetable code optimization techniques.
Presents a strong background and various perspectives of architecture description language (ADL)-based processor design and the retargetable compilation problem;
Provides the history of ADL based processor design, making the reader knowledgeable about the past research as well as the difficulties faced over time;
Offers an ADL based modelling formalism and corresponding implementation methods, which can be used for automatic compiler retargeting to quickly obtain compiler support for newly developed ASIPs;
Presents retargetable optimization techniques for common ASIP features, which can be quickly adapted to varying target processor configurations and help to meet the stringent performance requirements of embedded applications.