Amr M. Fahim

Clock Generators for Soc Processors

Circuits and Architectures

• Gebundenes Buch

Produktbeschreibung

This book examines the issue of design of fully-integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. This book takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The coverage of the book is comprehensive and includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discrete-time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior.
The book provides numerous real world applications, as well as practical rules-of-thumb for modern designers to use at the system, architectural, as well as the circuit level.

Produktdetails

• Verlag: Springer Netherlands
• Seitenzahl: 246
• Erscheinungstermin: 24. Juni 2005
• Englisch
• Abmessung: 240mm x 161mm x 20mm
• Gewicht: 572g
• ISBN-13: 9781402080791
• ISBN-10: 1402080794
• Artikelnr.: 21931685

Autorenporträt

Amr M. Fahim received his B.A.Sc, M.A.Sc, and Ph.D degrees from the University of Waterloo in Computer Engineering in 1996 and Electrical Engineering in 1997 and 2000, respectively. In 2000 he joined Qualcomm Inc., where he is currently working on the development of mixed-signal designs.  He is the author of over 20 papers and 5 patents in this area, and has been a reviewer for the IEEE Journal of Solid-State Circuits and IEEE Transactions on Circuits and Systems II.

Inhaltsangabe

Phase
Locked Loop Fundamentals.
Low
Voltage Analog Cmos Design.
Jitter Analysis in Phase
Locked Loops.
Low
Jitter PLL Architectures.
Digital PLL Design.
DSP Clock Generator Architectures.
Design for Testability in PLLs.
Clock Partitioning and Skew Control.