Andere Kunden interessierten sich auch für
![Approximate Arithmetic Circuit Architectures for FPGA-based Systems]( "Approximate Arithmetic Circuit Architectures for FPGA-based Systems")
Approximate Arithmetic Circuit Architectures for FPGA-based Systems59,99 €![Approximate Arithmetic Circuit Architectures for FPGA-based Systems]( "Approximate Arithmetic Circuit Architectures for FPGA-based Systems")
Approximate Arithmetic Circuit Architectures for FPGA-based Systems59,99 €![Design of Energy Efficient and Error Tolerant Approximate Multipliers]( "Design of Energy Efficient and Error Tolerant Approximate Multipliers")
Design of Energy Efficient and Error Tolerant Approximate Multipliers50,99 €![Low Power CMOS Approximate Voting Architecture for Reliable Computing]( "Low Power CMOS Approximate Voting Architecture for Reliable Computing")
Low Power CMOS Approximate Voting Architecture for Reliable Computing26,99 €![From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators]( "From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators")
From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators74,99 €![Design and implementation of low power and high performance filter]( "Design and implementation of low power and high performance filter")
Design and implementation of low power and high performance filter29,99 €![Design Of Low Power Approximate Adders]( "Design Of Low Power Approximate Adders")
Design Of Low Power Approximate Adders26,99 €
Approximate computation provide alternate solution to reduce energy consumption of high performance present day DSP application devices. Conventional multiplication and addition techniques consume a lot of energy. In this brief design of approximate arithmetic units for signal processing application is explored. First an approximate adder is proposed by changing the logic of basic full adder cell. The proposed adder cell has fewer transistor count compared to recent similar approach. Next, an approximate multiplier with low error is designed using lead one detection and selecting n/2 bits for an n bit input. The proposed n/2 bit approximate multiplier performs well in terms of error and power performance compared to recent similar approach. In continuation the approximate units are implemented in a Multiply-Accumulate(MAC) unit. The proposed approximate MAC unit provides significant improvement in power, area, and delay at the cost of little degrade in accuracy. Finally, the proposed MAC unit is implemented in filtering application to verify the functionality.
Hinweis: Dieser Artikel kann nur an eine deutsche Lieferadresse ausgeliefert werden.
Hinweis: Dieser Artikel kann nur an eine deutsche Lieferadresse ausgeliefert werden.