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One of the important biopotential signals is Electroencephalogram (EEG), which relates to electrical activity of human brain. The main characteristics of this signal are weak amplitude and low frequency, which generate difficulty to detect such signal. Basically, most EEG detection systems can be designed using CMOS process. The focus of this work will be on the amplification and filtering stages and the proposed design for the EEG detection system is called Analog Front-End (AFE) interleaved chain architecture. The proposed chain consists of three stages: the first and the third stages are instrumentation amplifier (IA) and programmable gain amplifier (PGA), respectively, and the second stage is notch filter with low pass feature. The proposed architecture relaxes the design of the notch filter and the analog-to-digital converter (ADC) used in the EEG detection system. A basic building block, which is proposed to realize the different stages of the AFE interleaved chain architecture, is the digitally programmable balanced output operational transconductance amplifier (DPOTA).