CMOS Low Power Analysis - Sharma, Vijay
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In this thesis leakage reduction techniques like stack forcing, multiple threshold CMOS, variable threshold CMOS are explored, that mitigate leakage in circuits, operating in the active mode at various temperatures. Also, implications of technology scaling on the choice of techniques to mitigate total leakage are closely examined. The result is guidelines for designing low-leakage circuits in nanometer technology nodes. Logic gates in the 180nm, 130nm, 100nm and 70nm technology nodes are simulated and analyzed. Here delay analysis of various logic circuits are also examined.

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Produktbeschreibung
In this thesis leakage reduction techniques like stack forcing, multiple threshold CMOS, variable threshold CMOS are explored, that mitigate leakage in circuits, operating in the active mode at various temperatures. Also, implications of technology scaling on the choice of techniques to mitigate total leakage are closely examined. The result is guidelines for designing low-leakage circuits in nanometer technology nodes. Logic gates in the 180nm, 130nm, 100nm and 70nm technology nodes are simulated and analyzed. Here delay analysis of various logic circuits are also examined.
Autorenporträt
El Dr. Vijay Sharma completó su investigación doctoral en la Universidad de Rajastán, India. Actualmente trabaja como profesor adjunto en el Departamento de Física del Government Mahila Engineering College, Ajmer, India. Tiene más de 18 años de experiencia en la enseñanza y la investigación. Es autor de más de 35 artículos de investigación en varias revistas de renombre.