Romain Wacquez

Constructive Side-Channel Analysis and Secure Design

15th International Workshop, COSADE 2024, Gardanne, France, April 9¿10, 2024, Proceedings
Herausgegeben:Homma, Naofumi

• Broschiertes Buch

Produktbeschreibung

This book constitutes the refereed proceedings of the 15th International Workshop on Constructive Side-Channel Analysis and Secure Design, COSADE 2024, held in Gardanne, France, during April 9-10, 2024.

The 14 full papers included in this book were carefully reviewed and selected from 42 submissions. They were organized in topical sections as follows: Analyses and Tools; Attack Methods; Deep-Learning-Based Side-Channel Attacks; PUF/RNG; and Cryptographic Implementations.

Produktdetails

• Lecture Notes in Computer Science 14595
• Verlag: Springer / Springer Nature Switzerland / Springer, Berlin
• Artikelnr. des Verlages: 978-3-031-57542-6
• 2024
• Seitenzahl: 292
• Erscheinungstermin: 17. April 2024
• Englisch
• Abmessung: 235mm x 155mm x 16mm
• Gewicht: 447g
• ISBN-13: 9783031575426
• ISBN-10: 3031575423
• Artikelnr.: 70022434

Inhaltsangabe

Analyses and Tools.- Characterizing and Modeling Synchronous Clock-Glitch Fault Injection.- On-chip evaluation of voltage drops and fault occurrence induced by Si backside EM injection.- EFFLUX-F2: A high performance hardware security evaluation board.- Attack Methods.- Practical Improvements to Statistical Ineffective Fault Attacks.- CAPABARA: A Combined Attack on CAPA.- Deep-Learning-Based Side-Channel Attacks.- Exploring Multi-Task Learning in the Context of Masked AES Implementations.- The Need for MORE: Unsupervised Side-channel Analysis with Single Network Training and Multi-output Regression.- Towards Private Deep Learning-Based Side-Channel Analysis using Homomorphic Encryption.- PUF/RNG.- Leakage Sources of the ICLooPUF: Analysis of a Side-Channel Protected Oscillator-Based PUF.- Impact of Process Mismatch and Device Aging on SR-Latch Based True Random Number Generators.- Lightweight Leakage-Resilient PRNG from TBCs using Superposition.- Cryptographic Implementations.- The Impact of Hash Primitives and Communication Overhead for Hardware-Accelerated SPHINCS+.- HaMAYO: A Fault-Tolerant Reconfigurable Hardware Implementation of the MAYO Signature Scheme.- Combining Loop Shuffling and Code Polymorphism for Enhanced AES Side-Channel Security.