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This book provides an overview of the circuits, architectures, and chip packaging for coupled data techniques. It discusses the current research in chip-to-board capacitive coupling, chip-to-chip capacitive coupling, chip-to-chip inductive coupling, and chip-to-chip optical coupling. Circuits, modeling, and their implications for packaging are explored in depth. Mechanical methods to ensure accurate and sustained chip alignment are discussed, as well as electrical methods to compensate for resulting misalignment. Finally, the book covers issues raised by design for manufacturing and…mehr

Produktbeschreibung
This book provides an overview of the circuits, architectures, and chip packaging for coupled data techniques. It discusses the current research in chip-to-board capacitive coupling, chip-to-chip capacitive coupling, chip-to-chip inductive coupling, and chip-to-chip optical coupling. Circuits, modeling, and their implications for packaging are explored in depth. Mechanical methods to ensure accurate and sustained chip alignment are discussed, as well as electrical methods to compensate for resulting misalignment. Finally, the book covers issues raised by design for manufacturing and test.

This book is one of the first in a new and emerging area. Coupled data communication offers new ways of looking at the old problem of limited off-chip I/O: it trades off packaging complexity for I/O performance; it offers a set of enabling technologies for 3D or stacked-chip architectures; and it raises the possibility of replace-able chips--and thus high yield--in an MCM.
Wafer-scale integration has long been the dream of system designers. Instead of chopping a wafer into a few hundred or a few thousand chips, one would just connect the circuits on the entire wafer. What an enormous capability wafer-scale integration would offer: all those millions of circuits connected by high-speed on-chip wires. Unfortunately, the best known optical systems can provide suitably ?ne resolution only over an area much smaller than a whole wafer. There is no known way to pattern a whole wafer with transistors and wires small enough for modern circuits. Statistical defects present a ?rmer barrier to wafer-scale integration. Flaws appear regularly in integrated circuits; the larger the circuit area, the more probable there is a ?aw. If such ?aws were the result only of dust one might reduce their numbers, but ?aws are also the inevitable result of small scale. Each feature on a modern integrated circuit is carved out by only a small number of photons in the lithographic process. Each transistor gets its electrical properties from only a small number of impurity atoms in its tiny area. Inevitably, the quantized nature of light and the atomic nature of matter produce statistical variations in both the number of photons de?ning each tiny shape and the number of atoms providing the electrical behavior of tiny transistors. No known way exists to eliminate such statistical variation, nor may any be possible.