Andere Kunden interessierten sich auch für
![Two-Tone PLL]( "Two-Tone PLL")
Two-Tone PLL32,99 €![INTER-CONNECTED FLEXRAY AND CAN NETWORKS FOR IN-VEHICLE COMMUNICATION]( "INTER-CONNECTED FLEXRAY AND CAN NETWORKS FOR IN-VEHICLE COMMUNICATION")
INTER-CONNECTED FLEXRAY AND CAN NETWORKS FOR IN-VEHICLE COMMUNICATION51,99 €![Wired and Wireless Inter-Chip and Intra-Chip Communications]( "Wired and Wireless Inter-Chip and Intra-Chip Communications")
Wired and Wireless Inter-Chip and Intra-Chip Communications53,90 €![An Innovative Approach of Low cost CP-PLL DFT Design]( "An Innovative Approach of Low cost CP-PLL DFT Design")
An Innovative Approach of Low cost CP-PLL DFT Design38,99 €![PLL Performance, Simulation, and Design]( "PLL Performance, Simulation, and Design")
PLL Performance, Simulation, and Design192,99 €![Design of PLL using Ring VCO]( "Design of PLL using Ring VCO")
Design of PLL using Ring VCO26,99 €![The impact of inter-vehicle communication on vehicular traffic]( "The impact of inter-vehicle communication on vehicular traffic")
The impact of inter-vehicle communication on vehicular traffic38,50 €
This work describes the design and implementation of a fully monolithic 10 Gb/s phase and frequency-locked loop based clock and data recovery (PFLL-CDR) integrated circuit, as well as the Verilog-A modeling of an asynchronous serial link based chip to chip communication system incorporating the proposed concept. The frequency-locked loop (FLL) operates independently from the phase-locked loop (PLL), and has a highly-desired feature that once the proper frequency has been acquired, the FLL is automatically disabled and the PLL will take over to adjust the clock edges approximately in the middle of the incoming data bits for proper sampling. Another important feature of the proposed quarter-rate concept is the inherent 1-to-4 demultiplexing of the input serial data stream. In order to verify the accuracy of the proposed quarter-rate concept, a clockless asynchronous serial link incorporating the proposed concept and communicating two chips at 10 Gb/s has been modeled at gate level using the Verilog-A language and time-domain simulated.