Sung Kyu Lim

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

• Broschiertes Buch

Produktbeschreibung

This book provides readers with a variety of algorithms and software tools, dedicated to the physical design of through-silicon-via (TSV) based, three-dimensional integrated circuits. It describes numerous "manufacturing-ready" GDSII-level layouts of TSV-based 3D ICs developed with the tools covered in the book. This book will also feature sign-off level analysis of timing, power, signal integrity, and thermal analysis for 3D IC designs. Full details of the related algorithms will be provided so that the readers will be able not only to grasp the core mechanics of the physical design tools, but also to be able to reproduce and improve upon the results themselves. This book will also offer various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the physical design process.

Produktdetails

• Verlag: Springer / Springer New York / Springer, Berlin
• Artikelnr. des Verlages: 978-1-4899-8696-2
• 2013
• Seitenzahl: 588
• Erscheinungstermin: 16. Dezember 2014
• Englisch
• Abmessung: 235mm x 155mm x 32mm
• Gewicht: 908g
• ISBN-13: 9781489986962
• ISBN-10: 1489986960
• Artikelnr.: 41906203

Inhaltsangabe

Regular vs Irregular TSV Placementfor 3D IC.- Steiner Routingfor 3D IC.- Buffer Insertion for 3D IC.- Low Power Clock Routing for 3D IC.- Power Delivery Network Design for 3D IC.- 3D Clock Routing for Pre-bond Testability.- TSV-to-TSV Coupling Analysis and Optimization.- TSV Current Crowding and Power Integrity.- Modeling of Atomic Concentration at the Wire-to-TSV Interface.- Multi-Objective Archetectural Floorplanning for 3D IC.- Thermal-aware Gate-level Placement for 3D IC.- 3D IC Cooling with Micro-Fluidic Channels.- Mechanical Reliability Analysis and Optimization for 3D IC.- Impact of Mechanical Stress on Timing Variation for 3D IC.- Chip/Package Co-Analysis of Mechanical Stress for 3D IC.- 3D Chip/Packaging Co-Analysis of Stress-Induced Timing Variations.- TSV Interfracial Crack Analysis and Optimization.- Ultra High Logic Designs Using Monolithic 3D Integration.- Impact of TSV Scaling on 3D IC Design Quality.- 3D-MAPS: 3DMassively Parallel Processor with Stacked Memory.