Andere Kunden interessierten sich auch für
![High Performance Comparator Design using Hybrid PTL/CMOS Logic Style]( "High Performance Comparator Design using Hybrid PTL/CMOS Logic Style")
High Performance Comparator Design using Hybrid PTL/CMOS Logic Style26,99 €![Minimization of Dynamic Power Through Structural Changes &Vt Techniques]( "Minimization of Dynamic Power Through Structural Changes &Vt Techniques")
Minimization of Dynamic Power Through Structural Changes &Vt Techniques50,99 €![Design & Analysis of Low Power VCO for VLSI & Communication System]( "Design & Analysis of Low Power VCO for VLSI & Communication System")
Design & Analysis of Low Power VCO for VLSI & Communication System36,99 €![Low Power Operational Transconductance Amplifier]( "Low Power Operational Transconductance Amplifier")
Low Power Operational Transconductance Amplifier23,99 €![Design Of Low Power Approximate Adders]( "Design Of Low Power Approximate Adders")
Design Of Low Power Approximate Adders23,99 €![Design and Gain Investigation of two Stage Operational Amplifiers]( "Design and Gain Investigation of two Stage Operational Amplifiers")
Design and Gain Investigation of two Stage Operational Amplifiers36,99 €![Design and Optimisation of Carry Select Adder]( "Design and Optimisation of Carry Select Adder")
Design and Optimisation of Carry Select Adder26,99 €
The design of 64-bit parallel prefix adder using transmission gate which acquires least number of nodes with the lowest transistor count and low power consumption has been addressed in this book. The 64-bit parallel prefix adder is designed and comparison is made among previous parallel prefix adders. The result shows that the proposed 64-bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the speed. The proposed parallel prefix adders consumes less power and implements lesser number of transistors compared to existing parallel prefix adders.