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Laterally Double Diffused MOSFET (LDMOS), a medium power semiconducting device, finds its place as a key amplifying device in RF Power Amplifiers and switching device in Power Management Circuits in System on Chips (SOC). The increasing market in these areas fuelled the research of these devices, and hence device level optimization of LDMOS gained key importance. This work solves three main challenges, as follows, 1) Can a non-linear semiconducting device like LDMOS, be made as an ideal amplifying device with linear transfer characteristics? 2) Can the breakdown voltage be increased in thin film SOI LDMOS, without the expense of other performance parameters? 3) Can scaling continue for better Power Performance & Area (PPA) in SOI technology, without degrading the high voltage operation of Fully Depleted SOI LDMOS?. All the above mentioned challenges are systematically studied and analyzed. New device architectures are also proposed to enhance the device performance and substantiated with extensive TCAD device simulations.