DAVID LILJA received his PhD in Electrical Engineering from the University of Illinois at Urbana-Champaign. He is currently a Professor of Electrical and Computer Engineering , and a Fellow of the Minnesota Supercomputing Institute, at the University of Minnesota in Minneapolis. He also serves as a member of the graduate faculties in Computer Science and Scientific Computation, and was the founding Director of Graduate Studies for Computer Engineering. He has served on the program committees of numerous conferences and as associate editor for IEEE Transactions on Computers. David is a Senior member of the IEEE and a member of the ACM.
Preface
1. Controlling complexity
2. A verilogical place to start
3. Defining the instruction set architecture
4. Algorithmic behavioral modeling
5. Building an assembler for VeSPA
6. Pipelining
7. Implementation of the pipelined processor
8. Verification
Appendix A: the VeSPA instruction set architecture (ISA)
Appendix B: the VASM assembler
Index.
