DUAL SLEEP APPROACH TO VLSI DESIGN
A NOVEL APPROACH TO LOW LEAKAGE AND AREA EFFICIENT VLSI DESIGN
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For the most recent CMOS technology feature sizes (e.g., 90nm and 65nm and less), leakage power dissipation has become a major concern. According to the International Technology Roadmap for Semiconductors (ITRS), leakage power dissipation may come to dominate total power consumption as technology feature sizes shrink. We propose a new method called dual sleep method which reduces leakage current and saves area in a considerable amount. It also saves exact logic state which makes it better than traditional sleep and zigzag techniques. Unlike the stack approach (which saves state), this approach...
For the most recent CMOS technology feature sizes (e.g., 90nm and 65nm and less), leakage power dissipation has become a major concern. According to the International Technology Roadmap for Semiconductors (ITRS), leakage power dissipation may come to dominate total power consumption as technology feature sizes shrink. We propose a new method called dual sleep method which reduces leakage current and saves area in a considerable amount. It also saves exact logic state which makes it better than traditional sleep and zigzag techniques. Unlike the stack approach (which saves state), this approach can work well with dual-Vth technologies, reducing leakage by several orders of magnitude over the stack approach in single-Vth technology. In comparison with the most common approaches in VLSI design (sleepy stack and sleepy keeper approaches), the dual sleep method serves better leakage power and dynamic power management than sleepy keeper and better speed than sleepy stack. Moreover, thearea required by dual sleep method is much less than those of the sleepy stack and sleepy keeper approaches.
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