Dynamic Task Allocation and Scheduling for Network-on-Chip Systems - Paul, Suraj
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Traditional bus based System-on-Chip (SoC) designs show limited performance, higher latency and power consumption. Network-on-Chip (NoC) has evolved as a promising technique to overcome these bottleneck posed by SoC designs. In NoC paradigm, the processing elements communicate with each other using a router based packet switched network which is scalable, flexible and reusable. In such NoC based multi-core systems, task allocation and scheduling is a challenging problem. It directly affects the performance of the application in terms of communication energy consumption and timing. The…mehr

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Produktbeschreibung
Traditional bus based System-on-Chip (SoC) designs show limited performance, higher latency and power consumption. Network-on-Chip (NoC) has evolved as a promising technique to overcome these bottleneck posed by SoC designs. In NoC paradigm, the processing elements communicate with each other using a router based packet switched network which is scalable, flexible and reusable. In such NoC based multi-core systems, task allocation and scheduling is a challenging problem. It directly affects the performance of the application in terms of communication energy consumption and timing. The complexity of the problem increases further for dynamic scenarios where new applications can arrive or exit the multi-core platform at any time instant. In real-time systems, validity of computation is dependent on both the correctness of the results and temporal constraint satisfaction. Although a significant amount of work has been done in the domain of task allocation, existing algorithms either do not address task scheduling along with mapping or assume an as-soon-as-possible scheduling strategy to determine task allocation at design-time.
Autorenporträt
Suraj Paul received his B. Tech. degree in Electronics and Communication Engineeringfrom National Institute of Technology, Durgapur, India, in 2009 and M.Tech degree from Indian Institute of Technology, Kharagpur, India, in 2016. His research interest includes embedded system design, real-time processing and multi/many-core platforms