The work described in this book, composed of two parts, aims at providing models, methodologies and tools to support each step of the co-design flow of embedded systems implemented by exploiting heterogeneous multi-processor architectures mapped on distributed systems, as well as fully integrated onto a single chip.
The work described in this book, composed of two parts, aims at providing models, methodologies and tools to support each step of the co-design flow of embedded systems implemented by exploiting heterogeneous multi-processor architectures mapped on distributed systems, as well as fully integrated onto a single chip.Hinweis: Dieser Artikel kann nur an eine deutsche Lieferadresse ausgeliefert werden.
Preface Acknowledgments List of Figures List of Tables List of Abbreviations Part 1: System Level Co Design of Heterogeneous Multi Processor Embedded Systems 1 Introduction 2 Background 3 The Proposed Approach 4 System Level Co Specification 5 Metrics for Co Analysis 6 System Level Co Estimations 7 System Level Partitioning 8 System Level Co Simulation 9 Case Studies Conclusions (Part 1) Part 2 10 System Level Design Space Exploration 11 SystemC Based ESL Design Space Exploration References Index About the Author
Preface Acknowledgments List of Figures List of Tables List of Abbreviations Part 1: System Level Co Design of Heterogeneous Multi Processor Embedded Systems 1 Introduction 2 Background 3 The Proposed Approach 4 System Level Co Specification 5 Metrics for Co Analysis 6 System Level Co Estimations 7 System Level Partitioning 8 System Level Co Simulation 9 Case Studies Conclusions (Part 1) Part 2 10 System Level Design Space Exploration 11 SystemC Based ESL Design Space Exploration References Index About the Author
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