Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces

High Performance Compute and System-In-Package
Herausgegeben:Keser, Beth; Kröhnert, Steffen

• Gebundenes Buch

Produktbeschreibung

Discover an up-to-date exploration of Embedded and Fan-Out Waver and Panel Level technologies

In Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces: High Performance Compute and System-in-Package, a team of accomplished semiconductor experts delivers an in-depth treatment of various fan-out and embedded die approaches.

The book begins with a market analysis of the latest technology trends in Fan-Out and Wafer Level Packaging before moving on to a cost analysis of these solutions. The contributors discuss the new package types for advanced application spaces being created by companies like TSMC, Deca Technologies, and ASE Group. Finally, emerging technologies from academia are explored.

Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces is an indispensable resource for microelectronic package engineers, managers, and decision makers working with OEMs and IDMs. It is also a must-read for professors and graduate students working in microelectronics packaging research.

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Produktdetails

• Wiley - IEEE
• Verlag: Wiley / Wiley & Sons
• Artikelnr. des Verlages: 1W119793770
• 1. Auflage
• Seitenzahl: 320
• Erscheinungstermin: 29. Dezember 2021
• Englisch
• Abmessung: 235mm x 157mm x 21mm
• Gewicht: 588g
• ISBN-13: 9781119793779
• ISBN-10: 1119793777
• Artikelnr.: 62570497

Autorenporträt

Beth Keser, PhD, is an IEEE Fellow and Distinguished Lecturer with over 23 years' experience in the semiconductor industry and a co-Editor of Advances in Embedded and Fan-Out Wafer Level Packaging Technologies. Beth's excellence in developing revolutionary electronic packages for semiconductor devices has resulted in 30 patents and patents pending and over 50 publications in the semiconductor industry. Steffen Kröhnert is President & Founder of ESPAT-Consulting in Dresden, Germany. He is member of IEE EPS and co-Editor of Advances in Embedded and Fan-Out Wafer Level Packaging Technologies. Steffen has over 20 years' experience in the semiconductor industry and is the author or co-author of 23 patent filings.

Inhaltsangabe

Preface xv

1 Fan-Out Wafer and Panel Level Packaging Market and Technology Trends 1
Santosh Kumar, Favier Shoo, and Stephane Elisabeth

1.1 Introduction to Fan-Out Packaging 1

1.1.1 Historical Perspective 1

1.1.2 Key Drivers: Why Fan-Out Packaging? 6

1.1.3 FO-WLP vs. FO-PLP 8

1.1.4 Future of Fan-Out Packaging for Heterogeneous Integration 8

1.2 Market Overview and Applications 10

1.2.1 Fan-Out Packaging Definition 10

1.2.2 Market Segmentation: Core FO vs. HD FO vs. UHD FO 11

1.2.3 Market Valuation: Forecast of Revenue and Volume 12

1.2.4 Current and Future Target Markets 12

1.2.5 Applications of Fan-Out Packaging 14

1.3 Technology Trends and Supply Chain 19

1.3.1 Fan-Out Packaging Technology Roadmaps 19

1.3.2 Fan-Out Packaging Technology by Manufacturer 19

1.3.2.1 Amkor 19

1.3.2.2 JCET 20

1.3.2.3 NXP 21

1.3.2.4 DECA Technologies 21

1.3.2.5 ASE 22

1.3.2.6 TSMC 22

1.3.2.7 PTI 24

1.3.2.8 Samsung Electronics 25

1.3.2.9 Huatian 25

1.3.3 Supply Chain Overview 25

1.3.4 Analysis of the Latest Developments in the Supply Chain 26

1.4 Fan-Out Panel-Level Packaging (FO-PLP) 29

1.4.1 Motivation and Challenges for FO-PLP 29

1.4.2 FO-PLP Market and Applications 30

1.4.3 FO-PLP Supplier Overview 31

1.5 SystemDevice Teardowns 34

1.5.1 Teardown of End-Systems with Fan-Out Packaging 34

1.5.2 Technology Comparison 38

1.5.2.1 Radar IC: eWLB vs. RCP 38

1.5.2.2 MCM/SiP: RCP-SiP vs. eWLB 39

1.5.2.3 PMIC: eWLB vs. M-Series 40

1.5.3 Cost Comparison 41

1.6 Conclusion 42

References 45

2 Cost Comparison of FO-WLP with Other Technologies 47
Amy Palesko Lujan

2.1 Introduction 47

2.2 Activity-Based Cost Modeling 47

2.3 Cost Analysis of FO-WLP Variations 49

2.3.1 Process Segment Costs 50

2.3.1.1 Die Preparation 50

2.3.1.2 Carrier 50

2.3.1.3 Die Bond 51

2.3.1.4 Mold 51

2.3.1.5 Backgrinding 51

2.3.1.6 RDL 51

2.3.1.7 UBM 52

2.3.1.8 Flux and Ball Attach 52

2.3.1.9 Singulation 52

2.3.2 FO-WLP Variations 52

2.3.2.1 Carrier 54

2.3.2.2 Die Cost and Preparation 54

2.3.2.3 Die Bond 54

2.3.2.4 Mold/Mold+CUF 54

2.3.2.5 Backgrind/Post-mold Grind 54

2.3.2.6 Scrap 55

2.4 Cost of FO-WLP versus Wire Bond and Flip Chip 55

2.5 Package-on-Package Cost Analysis 61

2.5.1.1 Substrate/RDLs 63

2.5.1.2 Die Bond 63

2.5.1.3 CUF and Mold Cost 63

2.5.1.4 Ball Attach 64

2.5.1.5 Singulation 64

2.5.1.6 TMV 64

2.5.1.7 Die Bond 66

2.5.1.8 CUF and Mold Cost 66

2.5.1.9 TMV/Large Copper Pillars 66

2.6 Conclusions 66

References 67

3 Integrated Fan-Out (InFO) for Mobile Computing 69
Doug C.H. Yu, John Yeh, Kuo-Chung Yee, and Chih Hang Tung

3.1 Introduction 69

3.2 Fan-InWafer-Level Packaging 70

3.2.1 Dielectric and Redistribution Layers (RDL) 71

3.2.2 Under Bump Metallization (UBM) 71

3.2.3 Reliability and Challenges 72

3.2.4 Large Die WLP 72

3.3 Fan-OutWafer-Level System Integration 73

3.3.1 Chip-First vs. Chip-Last 74

3.3.2 Molding and Planarization 75

3.3.3 Redistribution Layer (RDL) 77

3.3.4 Through Via