Embedded Computer Systems: Architectures, Modeling, and Simulation
24th International Conference, SAMOS 2024, Samos, Greece, June 29 - July 4, 2024, Proceedings, Part I Herausgegeben:Carro, Luigi; Regazzoni, Francesco; Pilato, Christian
Embedded Computer Systems: Architectures, Modeling, and Simulation
24th International Conference, SAMOS 2024, Samos, Greece, June 29 - July 4, 2024, Proceedings, Part I Herausgegeben:Carro, Luigi; Regazzoni, Francesco; Pilato, Christian
The two-volume set LNCS 15226 and 15227 constitutes the refereed proceedings of the 24th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2024, held in Samos, Greece, during June 29-July 4, 2024. The 24 full papers, 10 full papers in 2 special sessions and 4 poster session included in this book were carefully reviewed and selected from 57 submissions. This SAMOS 2024 covers the topics systems themselves - through their applications; architectures; and underlying processors - or methods created to automate their design.
The two-volume set LNCS 15226 and 15227 constitutes the refereed proceedings of the 24th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2024, held in Samos, Greece, during June 29-July 4, 2024.
The 24 full papers, 10 full papers in 2 special sessions and 4 poster session included in this book were carefully reviewed and selected from 57 submissions. This SAMOS 2024 covers the topics systems themselves - through their applications; architectures; and underlying processors - or methods created to automate their design.
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Inhaltsangabe
.- FAA+RTS: Designing Fault-Aware Adaptive Real-Time Systems - From Specification to Execution. .- Experimental Assessment and Biaffine Modeling of the Impact of Ambient Temperature on SoC Power Requirements. .- EPIC-Q : Equivalent-Policy Invariant Comparison enhanced transfer Q learning for run-time SoC performance-power optimization. .- Accelerating Depthwise Separable Convolutions on Ultra-Low-Power Devices. .- It's all about PR - Smart Benchmarking AI Accelerators using Performance Representatives. .- Travel Time-Based Task Mapping for NoC-Based DNN Accelerator. .- HW-EPOLL: Hardware-Assisted User Space Event Notification for Epoll Syscall. .- SIZALIZER: Multilevel Analysis Framework for Object Size Optimization. .- SafeFloatZone: Identify Safe Domains for Elementary Functions. .- Radar Object Detection on a Vector Processor using Sparse Convolutional Neural Networks. .- Optimizing QAM Demodulation with NEON SIMD and Algorithmic Ap proximation Techniques. .- A Novel Chaining-Based Indirect Addressing Mode in a Vertical Vector Processor. .- AutoSync Framework for expressing Synchronization Intentions in Multi threaded Programs. .- HyRPF: Hybrid RRAM Prototyping on FPGA. .- GLoRia: An Energy-Efficient GPU-RRAM System Stack for Large Neural Networks. .- Evaluating the Impact of Racetrack Memory Misalignment Faults on BNNs Performance. .- NanoSoftController: A Minimal Soft Processor for System State Control in FPGA Systems.
.- FAA+RTS: Designing Fault-Aware Adaptive Real-Time Systems - From Specification to Execution. .- Experimental Assessment and Biaffine Modeling of the Impact of Ambient Temperature on SoC Power Requirements. .- EPIC-Q : Equivalent-Policy Invariant Comparison enhanced transfer Q learning for run-time SoC performance-power optimization. .- Accelerating Depthwise Separable Convolutions on Ultra-Low-Power Devices. .- It's all about PR - Smart Benchmarking AI Accelerators using Performance Representatives. .- Travel Time-Based Task Mapping for NoC-Based DNN Accelerator. .- HW-EPOLL: Hardware-Assisted User Space Event Notification for Epoll Syscall. .- SIZALIZER: Multilevel Analysis Framework for Object Size Optimization. .- SafeFloatZone: Identify Safe Domains for Elementary Functions. .- Radar Object Detection on a Vector Processor using Sparse Convolutional Neural Networks. .- Optimizing QAM Demodulation with NEON SIMD and Algorithmic Ap proximation Techniques. .- A Novel Chaining-Based Indirect Addressing Mode in a Vertical Vector Processor. .- AutoSync Framework for expressing Synchronization Intentions in Multi threaded Programs. .- HyRPF: Hybrid RRAM Prototyping on FPGA. .- GLoRia: An Energy-Efficient GPU-RRAM System Stack for Large Neural Networks. .- Evaluating the Impact of Racetrack Memory Misalignment Faults on BNNs Performance. .- NanoSoftController: A Minimal Soft Processor for System State Control in FPGA Systems.
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