Emerging Nanoelectronic Devices

Herausgeber: Chen, An; Bourianoff, George; Zhirnov, Victor; Hutchby, James

• Gebundenes Buch

Produktbeschreibung

Emerging Nanoelectronic Devices focuses on the future direction of semiconductor and emerging nanoscale device technology. As the dimensional scaling of CMOS approaches its limits, alternate information processing devices and microarchitectures are being explored to sustain increasing functionality at decreasing cost into the indefinite future. This is driving new paradigms of information processing enabled by innovative new devices, circuits, and architectures, necessary to support an increasingly interconnected world through a rapidly evolving internet. This original title provides a fresh perspective on emerging research devices in 26 up to date chapters written by the leading researchers in their respective areas. It supplements and extends the work performed by the Emerging Research Devices working group of the International Technology Roadmap for Semiconductors (ITRS). Key features: * Serves as an authoritative tutorial on innovative devices and architectures that populate the dynamic world of "Beyond CMOS" technologies. * Provides a realistic assessment of the strengths, weaknesses and key unknowns associated with each technology. * Suggests guidelines for the directions of future development of each technology. * Emphasizes physical concepts over mathematical development. * Provides an essential resource for students, researchers and practicing engineers.

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Produktdetails

• Verlag: Wiley
• Seitenzahl: 576
• Erscheinungstermin: 27. Januar 2015
• Englisch
• Abmessung: 250mm x 175mm x 35mm
• Gewicht: 1156g
• ISBN-13: 9781118447741
• ISBN-10: 1118447743
• Artikelnr.: 41644040

Autorenporträt

An Chen is with GLOBALFOUNDRIES, working on emerging logic and memory technologies.  He is the Memory Technology Lead responsible for exploratory memory research with industrial consortia including IMEC and Sematech.  His memory research focuses primarily on RRAM and STTRAM.  Prior to GLOBALFOUNDRIES, he worked at Spansion LLC on emerging memory research and at Advanced Micro Devices (AMD) on nanoelectronics.  He is currently chairing the Emerging Research Device (ERD) working group in the International Technology Roadmap of Semiconductors (ITRS).  He is also a Senior Member of the IEEE.  James Hutchby, Senior Scientist, Emeritus, was formerly Director of Device Sciences of Semiconductor Research Corporation (SRC). Prior to joining SRC he was founding Director of the Research Triangle Institute's Center for Semiconductor Research, which consisted of five research groups performing research on: low-temperature growth of diamond; high efficiency multi-bandgap solar cells; complementary HBT devices and integrated circuits and high efficiency thermoelectrics and theremovoltaics. Dr Hutchby has authored or co-authored over 160 contributed and invited papers.  He is also a Life Fellow of the IEEE and a recipient of the IEEE Third Millennium Medal.  Victor Zhirnov is Director of Special Projects at the SRC. His research interests include nanoelectronics devices and systems, properties of materials at the nanoscale and bio-inspired electronic systems. He also holds an adjunct faculty position at North Carolina State University and has served as an advisor to a number of government, industrial, and academic institutions. Victor Zhirnov has authored and co-authored over 100 technical papers and contributions to books.  George Bourianoff is a Senior Principle Engineer in the Components Research group at Intel. He is responsible for developing and managing research programs in emerging research technologies and architectures.  He also serves on the scientific advisory boards of the Nanoelectronic Research Initiative (NRI) and the Semiconductor Technology Advanced Research Network. (STARnet).  Prior to joining Intel in 1994 Dr Bourianoff was a group leader in the Superconducting Supercollidier Project in Texas responsible for accelerator simulation.  Prior to that, he was a Senior Scientist with SAIC responsible for Magneto Hydrodynamic code development.

Inhaltsangabe

Preface xix
List of Contributors xxi
Acronyms xxiii
PART ONE INTRODUCTION 1
1 The Nanoelectronics Roadmap 3
James Hutchby
1.1 Introduction 3
1.2 Technology Scaling: Impact and Issues 4
1.3 Technology Scaling: Scaling Limits of Charge-based Devices 4
1.4 The International Technology Roadmap for Semiconductors 6
1.5 ITRS Emerging Research Devices International Technology Working Group 7
1.6 Guiding Performance Criteria 8
1.7 Selection of Nanodevices as Technology Entries 13
1.8 Perspectives 13
References 14
2 What Constitutes a Nanoswitch? A Perspective 15
Supriyo Datta, Vinh Quang Diep, and Behtash Behin-Aein
2.1 The Search for a Better Switch 15
2.2 Complementary Metal Oxide Semiconductor Switch: Why it Shows Gain 17
2.3 Switch Based on Magnetic Tunnel Junctions: Would it Show Gain? 20
2.4 Giant Spin Hall Effect: A Route to Gain 23
2.5 Other Possibilities for Switches with Gain 27
2.6 What do Alternative Switches Have to Offer? 29
2.7 Perspective 32
2.8 Summary 32
Acknowledgments 32
References 33
PART TWO NANOELECTRONIC MEMORIES 35
3 Memory Technologies: Status and Perspectives 37
Victor V. Zhirnov and Matthew J. Marinella
3.1 Introduction: Baseline Memory Technologies 37
3.2 Essential Physics of Charge-based Memory 38
3.3 Dynamic Random Access Memory 39
3.4 Flash Memory 43
3.5 Static Random Access Memory 49
3.6 Summary and Perspective 52
Appendix: Memory Array Interconnects 52
Acknowledgments 54
References 54
4 Spin Transfer Torque Random Access Memory 56
Jian-Ping Wang, Mahdi Jamali, Angeline Klemm, and Hao Meng
4.1 Chapter Overview 56
4.2 Spin Transfer Torque 57
4.3 STT-RAM Operation 60
4.4 STT-RAM with Perpendicular Anisotropy 63
4.5 Stack and Material Engineering for Jc Reduction 66
4.6 Ultra-Fast Switching of MTJs 71
4.7 Spin-Orbit Torques for Memory Application 72
4.8 Current Demonstrations for STT-RAM 73
4.9 Summary and Perspectives 73
References 74
5 Phase Change Memory 78
Rakesh Jeyasingh, Ethan C. Ahn, S. Burc Eryilmaz, Scott Fong, and H.-S.
Philip Wong
5.1 Introduction 78
5.2 Device Operation 79
5.3 Material Properties 80
5.4 Device and Material Scaling to the Nanometer Size 88
5.5 Multi-Bit Operation and 3D Integration 93
5.6 Applications 97
5.7 Future Outlook 100
5.8 Summary 103
Acknowledgments 103
References 103
6 Ferroelectric FET Memory 110
Ken Takeuchi and An Chen
6.1 Introduction 110
6.2 Ferroelectric FET for Flash Memory Application 111
6.3 Ferroelectric FET for SRAM Application 115
6.4 System Consideration: SSD System with Fe-NAND Flash Memory 118
6.5 Perspectives and Summary 119
References 120
7 Nano-Electro-Mechanical (NEM) Memory Devices 123
Adrian M. Ionescu
7.1 Introduction and Rationale for a Memory Based on NEM Switch 123
7.2 NEM Relay and Capacitor Memories 126
7.3 NEM-FET Memory 130
7.4 Carbon-based NEM Memories 132
7.5 Opportunities and Challenges for NEM Memories 133
References 135
8 Redox-based Resistive Memory 137
Stephan Menzel, Eike Linn, and Rainer Waser
8.1 Introduction 137
8.2 Physical Fundamentals of Redox Memories 139
8.3 Electrochemical Metallization Memory Cells 144
8.4 Valence Change Memory Cells 149
8.5 Performance 154
8.6 Summary 158
References 158
9 Electronic Effect Resistive Switching Memories 162
An Chen
9.1 Introduction 162
9.2 Charge Injection and Trapping 164
9.3 Mott Transition 167
9.4 Ferroelectric Resistive Switching 170
9.5 Perspectives 173
9.6 Summary 176
References 176
10 Macromolecular Memory 181
Benjamin F. Bory and Stefan C.J. Meskers
10.1 Chapter Overview 181
10.2 Macromolecules 181
10.3 Elementary Physical Chemistry of Macromolecular Memory 184
10.4 Classes of Macromolecular Memory Materials and Their Performance 187
10.5 Perspectives 190
10.6 Summary 190
Acknowledgments 190
References 191
11 Molecular Transistors 194
Mark A. Reed, Hyunwook Song, and Takhee Lee
11.1 Introduction 194
11.2 Experimental Approaches 194
11.3 Molecular Transistors 213
11.4 Molecular Design 218
11.5 Perspectives 222
Acknowledgments 223
References 223
12 Memory Select Devices 227
An Chen
12.1 Introduction 227
12.2 Crossbar Array and Memory Select Devices 227
12.3 Memory Select Device Options 230
12.4 Challenges of Memory Select Devices 241
12.5 Summary 242
References 242
13 Emerging Memory Devices: Assessment and Benchmarking 246
Matthew J. Marinella and Victor V. Zhirnov
13.1 Introduction 246
13.2 Common Emerging Memory Terminology and Metrics 248
13.3 Redox RAM 249
13.4 Emerging Ferroelectric Memories 254
13.5 Mott Memory 258
13.6 Macromolecular Memory 259
13.7 Carbon-based Resistive Switching Memory 260
13.8 Molecular Memory 262
13.9 Assessment and Benchmarking 263
13.10 Summary and Conclusions 271
Acknowledgments 271
References 271
PART THREE NANOELECTRONIC LOGIC AND INFORMATION PROCESSING 277
14 Re-Invention of FET 279
Toshiro Hiramoto
14.1 Introduction 279
14.2 Historical and Future Trend of MOSFETs 279
14.3 Near-term Solutions 282
14.4 Long-term Solutions 285
14.5 Summary 295
References 296
15 Graphene Electronics 298
Frank Schwierz
15.1 Introduction 298
15.2 Properties of Graphene 300
15.3 Graphene MOSFETs for Mainstream Logic and RF Applications 303
15.4 Graphene MOSFETs for Nonmainstream Applications 308
15.5 Graphene NonMOSFET Transistors 309
15.6 Perspectives 310
Acknowledgment 311
References 311
16 Carbon Nanotube Electronics 315
Aaron D. Franklin
16.1 Carbon Nanotubes - The Ideal Transistor Channel 315
16.2 Operation of the CNTFET 319
16.3 Important Aspects of CNTFETs 320
16.4 Scaling CNTFETs to the Sub-10 Nanometer Regime 324
16.5 Material Considerations 327
16.6 Perspective 329
16.7 Conclusion 331
References 331
17 Spintronics 336
Alexander Khitun
17.1 Introduction 336
17.2 Spin Transistors 337
17.3 Magnetic Logic Circuits 348
17.4 Summary 364
References 365
18 NEMS Switch Technology 370
Louis Hutin and Tsu-Jae King Liu
18.1 Electromechanical Switches for Digital Logic 370
18.2 Actuation Mechanisms 373
18.3 Electrostatic Switch Designs 379
18.4 Reliability and Scalability 383
References 386
19 Atomic Switch 390
Tsuyoshi Hasegawa and Masakazu Aono
19.1 Chapter Overview 390
19.2 Historical Background of the Atomic Switch 390
19.3 Fundamentals of Atomic Switches 391
19.4 Various Atomic Switches 395
19.5 Perspectives 401
References 402
20 ITRS Assessment and Benchmarking of Emerging Logic Devices 405
Shamik Das
20.1 Introduction 405
20.2 Overview of the ITRS Roadmap for Emerging Research Logic Devices 406
20.3 Recent Results for Selected Emerging Devices 407
20.4 Perspective 412
20.5 Summary 413
Acknowledgments 413
References 413
PART FOUR CONCEPTS FOR EMERGING ARCHITECTURES 417
21 Nanomagnet Logic: A Magnetic Implementation of Quantum-dot Cellular
Automata 419
Michael T. Niemier, György Csaba, and Wolfgang Porod
21.1 Introduction 419
21.2 Technology Background 420
21.3 NML Circuit Design Based on Conventional, Boolean Logic Gates 423
21.4 Alternative Circuit Design Techniques and Architectures 432
21.5 Retrospective, Future Challenges, and Future Research Directions 437
References 439
22 Explorations in Morphic Architectures 443
Tetsuya Asai and Ferdinand Peper
22.1 Introduction 443
22.2 Neuromorphic Architectures 443
22.3 Cellular Automata Architectures 447
22.4 Taxonomy of Computational Ability of Architectures 450
22.5 Summary 452
References 452
23 Design Considerations for a Computational Architecture of Human
Cognition 456
Narayan Srinivasa
23.1 Introduction 456
23.2 Features of Biological Computation 457
23.3 Evolution of Behavior as a Basis for Cognitive Architecture Design 460
23.4 Considerations for a Cognitive Architecture 460
23.5 Emergent Cognition 463
23.6 Perspectives 463
References 464
24 Alternative Architectures for NonBoolean Information Processing Systems
467
Yan Fang, Steven P. Levitan, Donald M. Chiarulli, and Denver H. Dash
24.1 Introduction 467
24.2 Hierarchical Associative Memory Models 475
24.3 N-Tree Model 484
24.4 Summary and Conclusion 494
Acknowledgments 496
References 496
25 Storage Class Memory 498
Geoffrey W. Burr and Paul Franzon
25.1 Introduction 498
25.2 Traditional Storage: HDD and Flash Solid-state Drives 499
25.3 What is Storage Class Memory? 499
25.4 Target Specifications for SCM 501
25.5 Device Candidates for SCM 502
25.6 Architectural Issues in SCM 504
25.7 Conclusions 508
References 509
PART FIVE SUMMARY, CONCLUSIONS, AND OUTLOOK FOR NANOELECTRONIC DEVICES 511
26 Outlook for Nanoelectronic Devices 513
An Chen, James Hutchby, Victor V. Zhirnov, and George Bourianoff
26.1 Introduction 513
26.2 Quantitative Logic Benchmarking for Beyond CMOS Technologies 514
26.3 Survey-based Critical Assessment of Emerging Devices 518
26.4 Retrospective Assessment of ERD Tracked Technologies 526
References 528
Index 529