Andere Kunden interessierten sich auch für
![Emerging Memory Technologies]( "Emerging Memory Technologies")
Emerging Memory Technologies74,99 €![Trace-Based Post-Silicon Validation for VLSI Circuits]( "Trace-Based Post-Silicon Validation for VLSI Circuits")
Trace-Based Post-Silicon Validation for VLSI Circuits74,99 €![Beyond-CMOS Technologies for Next Generation Computer Design]( "Beyond-CMOS Technologies for Next Generation Computer Design")
Beyond-CMOS Technologies for Next Generation Computer Design88,99 €![Beyond-CMOS Technologies for Next Generation Computer Design]( "Beyond-CMOS Technologies for Next Generation Computer Design")
Beyond-CMOS Technologies for Next Generation Computer Design88,99 €![Heterogeneous Memory Organizations in Embedded Systems]( "Heterogeneous Memory Organizations in Embedded Systems")
Heterogeneous Memory Organizations in Embedded Systems37,99 €![Heterogeneous Memory Organizations in Embedded Systems]( "Heterogeneous Memory Organizations in Embedded Systems")
Heterogeneous Memory Organizations in Embedded Systems37,99 €![On-Chip Current Sensors for Reliable, Secure, and Low-Power Integrated Circuits]( "On-Chip Current Sensors for Reliable, Secure, and Low-Power Integrated Circuits")
On-Chip Current Sensors for Reliable, Secure, and Low-Power Integrated Circuits42,99 €
This book equips readers with tools for computer architecture of high performance, low power, and high reliability memory hierarchy in computer systems based on emerging memory technologies, such as STTRAM, PCM, FBDRAM, etc. The techniques described offer advantages of high density, near-zero static power, and immunity to soft errors, which have the potential of overcoming the "memory wall." The authors discuss memory design from various perspectives: emerging memory technologies are employed in the memory hierarchy with novel architecture modification; hybrid memory structure is introduced to leverage advantages from multiple memory technologies; an analytical model named "Moguls" is introduced to explore quantitatively the optimization design of a memory hierarchy; finally, the vulnerability of the CMPs to radiation-based soft errors is improved by replacing different levels of on-chip memory with STT-RAMs.