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Recently, a variety of physical and chemical
methods have been used to synthesize and obtain 1-
dimensional semiconductor nanostructures. For the
cause of easier nanostructure formation and device
applications, we begin this study with the
investigation in growth mechanism and well-
controlled condition to synthesize 1-dimensional ZnO
nanowires.
For the low dimensional structure of nanowire,
the manipulation of individual nanowire has become
an unsettled and crucial issue. Therefore, we use a
printing method to realize the nanowire alignment in
broad classes. In addition, our investigators would
explore the correlation between the quality of 1-
dimensional material and electronic transport
properties of ZnO nanowire-based transistors.
In the fabrication of nanowire transistors, the
existing common method of dielectrophoresis (DEP)
process would impose a contact problem, and an
additional or subsequent metallization is necessary
for the electronic connection. Therefore, we will
develop a novel method to simultaneously obtain
aligned nanowire arrays and device pattering by
combining DEP and imprinting processes.
methods have been used to synthesize and obtain 1-
dimensional semiconductor nanostructures. For the
cause of easier nanostructure formation and device
applications, we begin this study with the
investigation in growth mechanism and well-
controlled condition to synthesize 1-dimensional ZnO
nanowires.
For the low dimensional structure of nanowire,
the manipulation of individual nanowire has become
an unsettled and crucial issue. Therefore, we use a
printing method to realize the nanowire alignment in
broad classes. In addition, our investigators would
explore the correlation between the quality of 1-
dimensional material and electronic transport
properties of ZnO nanowire-based transistors.
In the fabrication of nanowire transistors, the
existing common method of dielectrophoresis (DEP)
process would impose a contact problem, and an
additional or subsequent metallization is necessary
for the electronic connection. Therefore, we will
develop a novel method to simultaneously obtain
aligned nanowire arrays and device pattering by
combining DEP and imprinting processes.