FinFET/GAA Modeling for IC Simulation and Design - Chauhan, Yogesh Singh (Chair Professor, Department of Electrical Eng; Hu, Chenming (Professor Emeritus, University of California, Berkeley; Salahuddin, S.
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FinFET/GAA Modeling for IC Simulation and Design: Using the BSIM-CMG Standard, Second Edition is the first to book to explain FinFET modeling for IC simulation and the industry standard - BSIM-CMG - describing the rush in demand for advancing the technology from planar to 3D architecture as now enabled by the approved industry standard. The book gives a strong foundation on the physics and operation of FinFET, details aspects of the BSIM-CMG model such as surface potential, charge and current calculations, and includes a dedicated chapter on parameter extraction procedures, thus providing a…mehr

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Produktbeschreibung
FinFET/GAA Modeling for IC Simulation and Design: Using the BSIM-CMG Standard, Second Edition is the first to book to explain FinFET modeling for IC simulation and the industry standard - BSIM-CMG - describing the rush in demand for advancing the technology from planar to 3D architecture as now enabled by the approved industry standard. The book gives a strong foundation on the physics and operation of FinFET, details aspects of the BSIM-CMG model such as surface potential, charge and current calculations, and includes a dedicated chapter on parameter extraction procedures, thus providing a step-by-step approach for the efficient extraction of model parameters. With this book, users will learn Why you should use FinFET, The physics and operation of FinFET Details of the FinFET standard model (BSIM-CMG), Parameter extraction in BSIM-CMG FinFET circuit design and simulation, and more.
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Autorenporträt
Yogesh Singh Chauhan is a Chair professor in the department of electrical engineering at Indian Institute of Technology Kanpur, India. He is the developer of several industry standard models: ASM-HEMT, BSIM-BULK (formerly BSIM6), BSIM-CMG, BSIM-IMG, BSIM4 and BSIM-SOI models. His research group is involved in developing compact models for GaN transistors, FinFET, Nanosheet/Gate-All-Around FETs, FDSOI transistors, Negative Capacitance FETs and 2D FETs. His research interests are RF characterization, modeling, and simulation of semiconductor devices. He is the Fellow of IEEE and Indian National Academy of Engineering. He is the Editor of IEEE Transactions on Electron Devices and Distinguished Lecturer of the IEEE Electron Devices Society. He is the chairperson of IEEE U.P. section and IEEE-EDS Compact Modeling Committee. He has published more than 400 papers in international journals and conferences. He received Ramanujan fellowship in 2012, IBM faculty award in 2013 and P. K. Kelkar fellowship in 2015, CNR Rao faculty award, Humboldt fellowship and Swarnajayanti fellowship in 2018. He has served in the technical program committees of IEEE International Electron Devices Meeting (IEDM), IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), IEEE European Solid-State Device Research Conference (ESSDERC), IEEE Electron Devices Technology and Manufacturing (EDTM), and IEEE International Conference on VLSI Design and International Conference on Embedded Systems.