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Nowadays one of the most important design style for
Very Large Scale Intergrated (VLSI) circuits is
represented by Field Programmable Gate Arrays (FPGA).
Since their introduction in the early 90s, FPGAs
provided new challenges to the existing VLSI design
automation techniques.
FPGAs, due to their internal architecture, require
new techniques (or improvement to the existing ones)
for each step of the design ow. The oorplanning
automation for FPGAs is a current research topic, in
order to face the new challenges provided by FPGAs.
FPGAs presents two new aspects with respect to
classical VLSI design automation techniques: Resource
Heterogeneity and Reconfigurability.
This book focuses on the problem of nding an area
assignment for each module, i.e. nd an area where it
has to be con gured. Aim of this book is to provide a
formalization of the problem and an approach (divided
in three algorithms) to solve such problems. The
innovative contribution of this book consists in
facing area assignment problem taking concurrently
into account FPGAs heterogeneity and recon guration
limits. Furthermore the proposed approach takes into
account inter-module communication issues.
Very Large Scale Intergrated (VLSI) circuits is
represented by Field Programmable Gate Arrays (FPGA).
Since their introduction in the early 90s, FPGAs
provided new challenges to the existing VLSI design
automation techniques.
FPGAs, due to their internal architecture, require
new techniques (or improvement to the existing ones)
for each step of the design ow. The oorplanning
automation for FPGAs is a current research topic, in
order to face the new challenges provided by FPGAs.
FPGAs presents two new aspects with respect to
classical VLSI design automation techniques: Resource
Heterogeneity and Reconfigurability.
This book focuses on the problem of nding an area
assignment for each module, i.e. nd an area where it
has to be con gured. Aim of this book is to provide a
formalization of the problem and an approach (divided
in three algorithms) to solve such problems. The
innovative contribution of this book consists in
facing area assignment problem taking concurrently
into account FPGAs heterogeneity and recon guration
limits. Furthermore the proposed approach takes into
account inter-module communication issues.