Andere Kunden interessierten sich auch für
![Design of High Speed 32-Bit Floating Point FFT Processor using FPGA]( "Design of High Speed 32-Bit Floating Point FFT Processor using FPGA")
Design of High Speed 32-Bit Floating Point FFT Processor using FPGA29,99 €![64-bit RISC Processor using VHDL]( "64-bit RISC Processor using VHDL")
64-bit RISC Processor using VHDL32,99 €![IMPLEMENTIERUNG EINER HOCHLEISTUNGSFÄHIGEN 32-BIT RISC CORE ARCHITEKTUR]( "IMPLEMENTIERUNG EINER HOCHLEISTUNGSFÄHIGEN 32-BIT RISC CORE ARCHITEKTUR")
IMPLEMENTIERUNG EINER HOCHLEISTUNGSFÄHIGEN 32-BIT RISC CORE ARCHITEKTUR43,90 €![IMPLEMENTAZIONE DI UN'ARCHITETTURA CORE RISC A 32 BIT AD ALTE PRESTAZIONI]( "IMPLEMENTAZIONE DI UN'ARCHITETTURA CORE RISC A 32 BIT AD ALTE PRESTAZIONI")
IMPLEMENTAZIONE DI UN'ARCHITETTURA CORE RISC A 32 BIT AD ALTE PRESTAZIONI32,99 €![MISE EN ¿UVRE D'UNE ARCHITECTURE DE BASE 32 BITS RISC À HAUTE PERFORMANCE]( "MISE EN ¿UVRE D'UNE ARCHITECTURE DE BASE 32 BITS RISC À HAUTE PERFORMANCE")
MISE EN ¿UVRE D'UNE ARCHITECTURE DE BASE 32 BITS RISC À HAUTE PERFORMANCE32,99 €![REALIZACIYa VYSOKOPROIZVODITEL'NOJ 32-RAZRYaDNOJ ARHITEKTURY YaDRA RISC]( "REALIZACIYa VYSOKOPROIZVODITEL'NOJ 32-RAZRYaDNOJ ARHITEKTURY YaDRA RISC")
REALIZACIYa VYSOKOPROIZVODITEL'NOJ 32-RAZRYaDNOJ ARHITEKTURY YaDRA RISC15,99 €![IMPLEMENTAÇÃO DE UMA ARQUITECTURA DE NÚCLEO RISC DE 32 BITS DE ELEVADO DESEMPENHO]( "IMPLEMENTAÇÃO DE UMA ARQUITECTURA DE NÚCLEO RISC DE 32 BITS DE ELEVADO DESEMPENHO")
IMPLEMENTAÇÃO DE UMA ARQUITECTURA DE NÚCLEO RISC DE 32 BITS DE ELEVADO DESEMPENHO32,99 €
The proposed FPGA based 64-bit RISC Communication Processor (RCP) design for developing the processor with 32 operations using pipeline feature is an efficient technique in which basic processor operations like arithmetic and logical unit, shifting unit, comparator unit based. And a special communication unit which has signal generation and transmission operations and application unit which consist of traffic light, digital clock generation and LFSR (linear feedback Shift Register) operations are been incorporated into the design of RCP. The RCP design is implemented using Virtex 7 using Verilog HDL and is compared with other FPGA members like Spartan 3E and Spartan 3A DSP.
Hinweis: Dieser Artikel kann nur an eine deutsche Lieferadresse ausgeliefert werden.
Hinweis: Dieser Artikel kann nur an eine deutsche Lieferadresse ausgeliefert werden.