Andere Kunden interessierten sich auch für
![An Efficient Implementation of High-Speed JPEG2000 Encoder/Decoder]( "An Efficient Implementation of High-Speed JPEG2000 Encoder/Decoder")
An Efficient Implementation of High-Speed JPEG2000 Encoder/Decoder38,99 €![MIMO CHANNEL ESTIMATION FOR FPGA IMPLEMENTATION]( "MIMO CHANNEL ESTIMATION FOR FPGA IMPLEMENTATION")
MIMO CHANNEL ESTIMATION FOR FPGA IMPLEMENTATION32,99 €![FPGA Implementation of LMMSE detector for MIMO OFDM System]( "FPGA Implementation of LMMSE detector for MIMO OFDM System")
FPGA Implementation of LMMSE detector for MIMO OFDM System32,99 €![Photonic Implementation of an Instantaneous Frequency Measurement]( "Photonic Implementation of an Instantaneous Frequency Measurement")
Photonic Implementation of an Instantaneous Frequency Measurement38,99 €![Smart Algorithms and Architectures for Real Time Video Transmission]( "Smart Algorithms and Architectures for Real Time Video Transmission")
Smart Algorithms and Architectures for Real Time Video Transmission51,99 €![FPGA Based Image Compression]( "FPGA Based Image Compression")
FPGA Based Image Compression38,99 €![FlexRay Applications in Control Loops Focussing on Steer-by-wire Models]( "FlexRay Applications in Control Loops Focussing on Steer-by-wire Models")
FlexRay Applications in Control Loops Focussing on Steer-by-wire Models32,99 €
The MPEG-2 video bitstream without any Scalable Modes is called the Base layer bitstream. The work involves designing the MPEG-2 video decoder and related interfacing logic for reading the MPEG file from flash memory, storing the decoded data in SDRAM and displaying the video on the SVGA monitor by reading the data from SRAM. We have used the C code as the reference, provided by the MPEG Software Simulation Groups. The bit-by-bit algorithm, for decoding the base layer Mpeg-2 video stream, was abstracted from the C code and the corresponding hardware module for decoding the sequence was designed in VHDL using Quartus 6.2 tool supplied by Altera. The designed decoder module takes the serial bit stream in MPEG-2 format from Flash Memory as input, parses the system layer and decodes the video data. The output is provided in 24 bit RGB form. The MPEG-2 file resides in the flash memory, from where it is read byte-by-byte by the decoder module. The decoded frame is written to the SRAM, which dual ported to act as VIDEO RAM or VRAM. The VGA controller reads continuously from the VRAM and displays the video on monitor. The design was implemented on DE1 university program" board.