Andere Kunden interessierten sich auch für
![Phase Locked Loop Design as a Frequency Multiplier]( "Phase Locked Loop Design as a Frequency Multiplier")
Phase Locked Loop Design as a Frequency Multiplier32,99 €![A Low Jitter ¿ Low Phase Noise Wideband Digital Phase Locked Loop]( "A Low Jitter ¿ Low Phase Noise Wideband Digital Phase Locked Loop")
A Low Jitter ¿ Low Phase Noise Wideband Digital Phase Locked Loop46,99 €![Low Power Phase Locked Loop With Multiple Output Using VLSI Technology]( "Low Power Phase Locked Loop With Multiple Output Using VLSI Technology")
Low Power Phase Locked Loop With Multiple Output Using VLSI Technology32,99 €![Optical Phase Locked Loop for Remote Carrier Signal Generation]( "Optical Phase Locked Loop for Remote Carrier Signal Generation")
Optical Phase Locked Loop for Remote Carrier Signal Generation36,99 €![Phase-locked loop]( "Phase-locked loop")
Phase-locked loop44,99 €![Phase Locked LOOP]( "Phase Locked LOOP")
Phase Locked LOOP26,99 €![Nanometer Frequency Synthesis Beyond the Phase-Locked Loop]( "Nanometer Frequency Synthesis Beyond the Phase-Locked Loop")
Nanometer Frequency Synthesis Beyond the Phase-Locked Loop162,99 €
All Digital Phase Locked Loops (ADPLLs) have become more attractive because they yield better testability, programmability, stability, and portability over different processes and the ADPLLs can reduce the system turn around time. Phase-locked loop mechanisms may be implemented as either analog or digital circuits. Both implementations use the same basic structure. The implemented ADPLL has two operation modes which are frequency acquisition mode and phase acquisition mode. In frequency acquisition mode, the ADPLL achieves a fast frequency locking via the proposed feed-forward compensation algorithm. In phase acquisition mode, the ADPLL achieves a finer phase locking.