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There have been many developments in the field of facilitated model based verification and validation techniques. Most of them have been based upon observing the external behaviour of the system. Our approach follows the same and is valid with the source code of the system under observance is not available Inference mechanism allow us to infer such machine models by observing. We present a framework which adopts to generate component with infinite/finite states and adapt to formal verifications. The models used are communication protocol inferred by regular inference observed through the…mehr

Produktbeschreibung
There have been many developments in the field of facilitated model based verification and validation techniques. Most of them have been based upon observing the external behaviour of the system. Our approach follows the same and is valid with the source code of the system under observance is not available Inference mechanism allow us to infer such machine models by observing. We present a framework which adopts to generate component with infinite/finite states and adapt to formal verifications. The models used are communication protocol inferred by regular inference observed through the behaviour of communication protocol entity. Also, an approach is presented such that the observed behaviour of the protocol validates to the designed model of the protocol.
Autorenporträt
Md Tanzilur Rahman is currently working as an Assistant professor and has done his Master's and Bachelor's in Engineering from Amity University, Noida, India and Jamia Hamdard University, India. He has interest's in following domains of research; Ad-Hoc Networks, Simulation Models, Artificial Intelligence, Software Testing and Software Development