This handbook presents fundamental knowledge on the hardware/software (HW/SW) codesign methodology. Contributing expert authors look at key techniques in the design flow as well as selected codesign tools and design environments, building on basic knowledge to consider the latest techniques. The book enables readers to gain real benefits from the HW/SW codesign methodology through explanations and case studies which demonstrate its usefulness. Readers are invited to follow the progress of design techniques through this work, which assists readers in following current research directions and…mehr
This handbook presents fundamental knowledge on the hardware/software (HW/SW) codesign methodology. Contributing expert authors look at key techniques in the design flow as well as selected codesign tools and design environments, building on basic knowledge to consider the latest techniques. The book enables readers to gain real benefits from the HW/SW codesign methodology through explanations and case studies which demonstrate its usefulness.
Readers are invited to follow the progress of design techniques through this work, which assists readers in following current research directions and learning about state-of-the-art techniques. Students and researchers will appreciate the wide spectrum of subjects that belong to the design methodology from this handbook.
Soonhoi Ha is currently a full professor in the School of Computer Science and Engineering at Seoul National University. From 1993 to 1994, he worked for Hyundai Electronics Industries Corporation. He received his Bachelors (1985) and Masters (1987) in Electronics Engineering from Seoul National University, and PhD (1992) degrees in Electrical Engineering and Computer Science from University of California, Berkeley. He has worked on the Ptolemy project and is now leading the PeaCE (development of a HW/SW codesign environment) and HOPES (development of an embedded S/W design environment for MPSoC) projects. His research interests include hardware-software codesign, design methodology for embedded systems and embedded S/W. He is a senior member of the IEEE Computer Society. Jürgen Teich (Senior Member, IEEE) received the M.S. degree (Dipl.-Ing.; with honors) from the University of Kaiserslautern, Germany, in 1989 and the Ph.D. degree (summa cum laude) from the University of Saarland, Saarbruecken, Germany, in 1993. In 1994, he joined the DSP design group of Prof. E. A. Lee in the Department of Electrical Engineering and Computer Sciences (EECS), University of California at Berkeley (PostDoc). From 1995 to 1998, he held a position at the Institute of Computer Engineering and Communications Networks Laboratory (TIK), ETH Zurich, Switzerland (Habilitation). From 1998 to 2002, he was Full Professor in the Electrical Engineering and Information Technology Department, University of Paderborn, Germany. Since 2003, he has been Full Professor in the Department of Computer Science, University of Erlangen-Nuremberg, Erlangen, Germany, holding a chair in Hardware/Software Co-Design. In 2011, he was elected member of the Academia Europaea. Since 2010, he has also been the coordinator of the Transregional Research Center 89 on Invasive Computing funded by the German Research Foundation (DFG).
Inhaltsangabe
Introduction to Hardware/Software Codesign
Quartz: A Synchronous Language for Model-Based Design of Reactive Embedded Systems
SysteMoC: A Data-Flow Programming Language for Codesign
ForSyDe: System Design Using a Functional Language and Models of Computation
Modeling Hardware/Software Embedded Systems with UML/MARTE: A Single-Source Design Approach
Optimization Strategies in Design Space Exploration
Hybrid Optimization Techniques for System-Level Design Space Exploration
Architecture and Cross-Layer Design Space Exploration
Scenario-Based Design Space Exploration
Design Space Exploration and Run-Time Adaptation for Multi-core Resource Management Under Performance and Power Constraints
Reconfigurable Architectures
Application-Specific Processors
Memory Architectures
Emerging and Non-volatile Memory
NOC-Based Multi-processor Architecture for Mi
xed Time-Criticality Applications
Parallel Simulation
Multi-processor System-on-Chip Prototyping Using Dynamic Binary Translation
