Debashis Bhattacharya, John P. Hayes

Hierarchical Modeling for VLSI Circuit Testing

• Gebundenes Buch

Produktbeschreibung

Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving theforegoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.

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Produktdetails

• The Springer International Series in Engineering and Computer Science 89
• Verlag: Springer / Springer US / Springer, Berlin
• Artikelnr. des Verlages: 978-0-7923-9058-9
• 1989.
• Seitenzahl: 160
• Erscheinungstermin: 31. Dezember 1989
• Englisch
• Abmessung: 234mm x 156mm x 11mm
• Gewicht: 940g
• ISBN-13: 9780792390589
• ISBN-10: 079239058X
• Artikelnr.: 24519180

Inhaltsangabe

1 Introduction.- 1.1 Background.- 1.2 Prior Work.- 1.3 Outline.- 2 Circuit and Fault Modeling.- 2.1 Vector Sequence Notation.- 2.2 Circuit and Fault Models.- 2.3 Case Study: k-Regular Circuits.- 3 Hierarchical Test Generation.- 3.1 Vector Cubes.- 3.2 Test Generation.- 3.3 Implementation and Experimental Results.- 4 Design for Testability.- 4.1 Ad Hoc Techniques.- 4.2 Level Separation (LS) Method.- 4.3 Case Study: ALU.- 5 Concluding Remarks.- 5.1 Summary.- 5.2 Future Directions.- Appendix A: Proofs of Theorems.- A.1 Proof of Theorem 3.2.- A.2 Proof of Theorem 3.3.- A.3 Proof of Theorem 4.1.