Beschreibung
Produktdetails
Einband
Taschenbuch
Verlag
VDMSeitenzahl
168
Maße (L/B/H)
22/15/1 cm
Gewicht
241 g
Sprache
Englisch
ISBN
978-3-639-09859-4
This book investigates the architecture design,
physical implementation, result evaluation, and
feature analysis of a many-core processor for DSP
applications. The system is composed of a 2-D array
of simple single-issue programmable processors
interconnected by a reconfigurable mesh network, and
processors operate completely asynchronously with
respect to each other in a Globally Asynchronous
Locally Synchronous fashion. The processor is called
Asynchronous Array of simple Processors (AsAP). A
6×6 array has been fabricated in a 0.18 µm CMOS
technology. The physical design concerns timing
issues for robust implementations, and takes full
advantages of their potential scalability. Each
processor occupies 0.66 mm², is fully functional at
a clock rate of 520 540 MHz under 1.8 V, and
dissipates 94 mW while the clock is 100% active.
The system is also easily scalable, and is well-
suited to future fabrication technologies.
physical implementation, result evaluation, and
feature analysis of a many-core processor for DSP
applications. The system is composed of a 2-D array
of simple single-issue programmable processors
interconnected by a reconfigurable mesh network, and
processors operate completely asynchronously with
respect to each other in a Globally Asynchronous
Locally Synchronous fashion. The processor is called
Asynchronous Array of simple Processors (AsAP). A
6×6 array has been fabricated in a 0.18 µm CMOS
technology. The physical design concerns timing
issues for robust implementations, and takes full
advantages of their potential scalability. Each
processor occupies 0.66 mm², is fully functional at
a clock rate of 520 540 MHz under 1.8 V, and
dissipates 94 mW while the clock is 100% active.
The system is also easily scalable, and is well-
suited to future fabrication technologies.
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