David A. Bader / Manish Parashar / V. Sridhar / Viktor K. Prasanna (eds.)

High Performance Computing - HiPC 2005

12th International Conference, Goa, India, December 18-21, 2005, Proceedings
Herausgegeben:Bader, David A.; Parashar, Manish; Sridhar, V.; Prasanna, Viktor K.

• Broschiertes Buch

Produktbeschreibung

to acknowledge the dedicated effort put forth by the Vice-Chairs: Michael A. Bender (Algorithms), Zhiwei Xu (Applications), Jose Duato (Architecture),M. Cristina Pinotti (Communication Networks), and Satoshi Matsuoka (System Software). Without their help and timely work, the quality of this program would not be as high nor would the process have run so smoothly. I thank the other organizers who have contributed to assembling this program, - cludingthose who organizedthe keynotes,tutorials, workshops,awards, poster session, industry exhibits, and those who performed the administrative functions that have been essential to the success of this conference. The work of Sushil K. Prasad in putting - gethertheconferenceproceedingsisalsoacknowledged,aswell asthesupportprovided by Kamesh Madduri and Vaddadi Chandu, Ph.D. students at Georgia Institute of Te- nology,and Vipin Sachdeva,M.S. student at the Universityof New Mexico, in assisting with the EDAS online paper submission and evaluation software. Last, but certainly not least, I express heart-felt thanks to our General Co-chairs, Manish Parashar and V. Sridhar; Steering Chair, Viktor Prasanna; and to the Vice-General Chair, Rajendra V. Boppana; for all their useful advice. Lastly, I thank the Conference General Co-chairs for allowing me to serve our c- munity as the Program Chair of this high-quality international conference. It has been my pleasure to correspond with so many of you, and I personally welcome you to Goa.

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Produktdetails

• Theoretical Computer Science and General Issues 3769
• Verlag: Springer / Springer Berlin Heidelberg / Springer, Berlin
• Artikelnr. des Verlages: 11602569, 978-3-540-30936-9
• 2005
• Seitenzahl: 584
• Erscheinungstermin: 9. Dezember 2005
• Englisch
• Abmessung: 235mm x 155mm x 32mm
• Gewicht: 871g
• ISBN-13: 9783540309369
• ISBN-10: 3540309365
• Artikelnr.: 22476080

Autorenporträt

Manish Parashar, PhD, is an associate professor in the Department of Electrical and Computer Engineering at Rutgers, The State University of New Jersey, where he is Director of The Applied Software Systems Laboratory (TASSL). Professor Parashar is a recipient of the NSF CAREER award and the Enrico Fermi scholarship, and is a senior member of the IEEE. In addition to publishing over a hundred technical papers in international journals and conferences, Professor Parashar has coauthored/edited three books, and has contributed to several others, in the area of parallel and distributed computing.

Inhaltsangabe

Keynote Addresses.- Data Confidentiality in Collaborative Computing.- Productivity in High Performance Computing.- A New Approach to Programming and Prototyping Parallel Systems.- The Changing Challenges of Collaborative Algorithmics.- Quantum Physics and the Nature of Computation.- Plenary Session - Best Papers.- Preemption Adaptivity in Time-Published Queue-Based Spin Locks.- Criticality Driven Energy Aware Speculation for Speculative Multithreaded Processors.- Session I - Algorithms.- Search-Optimized Suffix-Tree Storage for Biological Applications.- Cost-Optimal Job Allocation Schemes for Bandwidth-Constrained Distributed Computing Systems.- A Fault Recovery Scheme for P2P Metacomputers.- A Distributed Location Identification Algorithm for Ad hoc Networks Using Computational Geometric Methods.- A Symmetric Localization Algorithm for MANETs Based on Collapsing Coordinate Systems.- Session II - Applications.- Performance Study of LU Decomposition on the Programmable GPU.- PENCAPS: A Parallel Application for Electrode Encased Grounding Systems Project.- Application of Reduce Order Modeling to Time Parallelization.- Orthogonal Decision Trees for Resource-Constrained Physiological Data Stream Monitoring Using Mobile Devices.- Throughput Computing with Chip MultiThreading and Clusters.- Session III - Architecture.- Supporting MPI-2 One Sided Communication on Multi-rail InfiniBand Clusters: Design Challenges and Performance Benefits.- High Performance RDMA Based All-to-All Broadcast for InfiniBand Clusters.- Providing Full QoS Support in Clusters Using Only Two VCs at the Switches.- Offloading Bloom Filter Operations to Network Processor for Parallel Query Processing in Cluster of Workstations.- A High-Speed VLSI Array Architecture for Euclidean Metric-Based Hausdorff Distance Measures Between Images.- Session IV - Applications.- Sensor Selection Heuristic in Sensor Networks.- Mobile Pipelines: Parallelizing Left-Looking Algorithms Using Navigational Programming.- Distributed Point Rendering.- An Intra-task DVS Algorithm Exploiting Program Path Locality for Real-Time Embedded Systems.- Advanced Resource Management and Scheduling of Workflow Applications in JavaSymphony.- Session V - Systems Software.- Using Clustering to Address Heterogeneity and Dynamism in Parallel Scientific Applications.- Data and Computation Abstractions for Dynamic and Irregular Computations.- XCAT-C++: Design and Performance of a Distributed CCA Framework.- The Impact of Noise on the Scaling of Collectives: A Theoretical Approach.- Extensible Parallel Architectural Skeletons.- Session VI - Communication Networks.- An Efficient Distributed Algorithm for Finding Virtual Backbones in Wireless Ad-Hoc Networks.- A Novel Battery Aware MAC Protocol for Minimizing Energy × Latency in Wireless Sensor Networks.- On the Power Optimization and Throughput Performance of Multihop Wireless Network Architectures.- A Novel Solution for Time Synchronization in Wireless Ad Hoc and Sensor Networks.- An Algorithm for Boundary Discovery in Wireless Sensor Networks.- Session VII - Architecture.- A Low-Complexity Issue Queue Design with Speculative Pre-execution.- Performance and Power Evaluation of an Intelligently Adaptive Data Cache.- Neural Confidence Estimation for More Accurate Value Prediction.- The Potential of On-Chip Multiprocessing for QCD Machines.- Low-Power 32bit×32bit Multiplier Design with Pipelined Block-Wise Shutdown.- Session VIII - Communication Networks.- Performance Analysis of User-Level PIM Communication in the Data IntensiVe Architecture (DIVA) System.-Improved Point-to-Point and Collective Communication Performance with Output-Queued High-Radix Routers.- A Clustering and Traffic-Redistribution Scheme for High-Performance IPsec VPNs.- WDM Multistage Interconnection Networks Architectures for Enhancing Supernetworks Switching Infrastructure.- Learning-TCP: A Novel Learning Automata Based Congestion Window Updating Mechanism for Ad hoc Wireless Networks.- Session IX - Algorithms.- Design and Implementation of the HPCS Graph Analysis Benchmark on Symmetric Multiprocessors.- Scheduling Multiple Flows on Parallel Disks.- Snap-Stabilizing Detection of Cutsets.- Scheduling Divisible Loads with Return Messages on Heterogeneous Master-Worker Platforms.- Session X - Systems and Networks.- A Grid Authentication System with Revocation Guarantees.- Integrating a New Cluster Assignment and Scheduling Algorithm into an Experimental Retargetable Code Generation Framework.- Cooperative Instruction Scheduling with Linear Scan Register Allocation.- iSCSI Analysis System and Performance Improvement of iSCSI Sequential Access in High Latency Networks.