This book constitutes the refereed proceedings of the Fourth International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The 27 revised full papers presented together with 2 invited keynote paper were carefully reviewed and selected from 97 submissions. The papers are organized in topical sections on dynamic translation and optimisation, low level scheduling, parallelism and resource control, communication, mapping for CMPs, power, cache issues as well as parallel embedded applications.
This book constitutes the refereed proceedings of the Fourth International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The 27 revised full papers presented together with 2 invited keynote paper were carefully reviewed and selected from 97 submissions. The papers are organized in topical sections on dynamic translation and optimisation, low level scheduling, parallelism and resource control, communication, mapping for CMPs, power, cache issues as well as parallel embedded applications.
Produktdetails
Produktdetails
Theoretical Computer Science and General Issues 5409
Artikelnr. des Verlages: 12601547, 978-3-540-92989-5
2009
Seitenzahl: 436
Erscheinungstermin: 12. Januar 2009
Englisch
Abmessung: 235mm x 155mm x 24mm
Gewicht: 656g
ISBN-13: 9783540929895
ISBN-10: 3540929894
Artikelnr.: 25700825
Herstellerkennzeichnung
Die Herstellerinformationen sind derzeit nicht verfügbar.
Autorenporträt
Prof. Dr. Theo Ungerer ist Professor für Systemnahe Informatik mit Schwerpunkt Kommunikationssysteme und Internet-Anwendungen am Institut für Informatik der Universität Augsburg. Zudem ist er wissenschaftlicher Direktor des Rechenzentrums und Mitglied des Lenkungsrates des IT-Servicezentrums der Universität Augsburg. Seine wissenschaftlichen Interessen gelten den Gebieten der Prozessorarchitektur sowie der eingebetteten und ubiquitären Systeme. Theo Ungerer hat über 150 wissenschaftliche Publikationen und 6 Fachbücher veröffentlicht. Er ist Mitglied des Lenkungsrates und deutscher Koordinator des EU-Exzellenznetzwerkes HiPEAC- High Performance Embedded Architectures and Compilers
Inhaltsangabe
Invited Program.- Keynote: Challenges on the Road to Exascale Computing.- Keynote: Compilers in the Manycore Era.- I Dynamic Translation and Optimisation.- Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering.- Predictive Runtime Code Scheduling for Heterogeneous Architectures.- Collective Optimization.- High Speed CPU Simulation Using LTU Dynamic Binary Translation.- II Low Level Scheduling.- Integrated Modulo Scheduling for Clustered VLIW Architectures.- Software Pipelining in Nested Loops with Prolog-Epilog Merging.- A Flexible Code Compression Scheme Using Partitioned Look-Up Tables.- III Parallelism and Resource Control.- MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor.- IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor.- A Hardware Task Scheduler for Embedded Video Processing.- Finding Stress Patterns in Microprocessor Workloads.- IV Communication.- Deriving Efficient Data Movement from Decoupled Access/Execute Specifications.- MPSoC Design Using Application-Specific Architecturally Visible Communication.- Communication Based Proactive Link Power Management.- V Mapping for CMPs.- Mapping and Synchronizing Streaming Applications on Cell Processors.- Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors.- Accomodating Diversity in CMPs with Heterogeneous Frequencies.- A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip.- VI Power.- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture.- Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines.- HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic.- Compiler Controlled Speculationfor Power Aware ILP Extraction in Dataflow Architectures.- VII Cache Issues.- Revisiting Cache Block Superloading.- ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors.- In-Network Caching for Chip Multiprocessors.- VIII Parallel Embedded Applications.- Parallel LDPC Decoding on the Cell/B.E. Processor.- Parallel H.264 Decoding on an Embedded Multicore Processor.
Invited Program.- Keynote: Challenges on the Road to Exascale Computing.- Keynote: Compilers in the Manycore Era.- I Dynamic Translation and Optimisation.- Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering.- Predictive Runtime Code Scheduling for Heterogeneous Architectures.- Collective Optimization.- High Speed CPU Simulation Using LTU Dynamic Binary Translation.- II Low Level Scheduling.- Integrated Modulo Scheduling for Clustered VLIW Architectures.- Software Pipelining in Nested Loops with Prolog-Epilog Merging.- A Flexible Code Compression Scheme Using Partitioned Look-Up Tables.- III Parallelism and Resource Control.- MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor.- IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor.- A Hardware Task Scheduler for Embedded Video Processing.- Finding Stress Patterns in Microprocessor Workloads.- IV Communication.- Deriving Efficient Data Movement from Decoupled Access/Execute Specifications.- MPSoC Design Using Application-Specific Architecturally Visible Communication.- Communication Based Proactive Link Power Management.- V Mapping for CMPs.- Mapping and Synchronizing Streaming Applications on Cell Processors.- Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors.- Accomodating Diversity in CMPs with Heterogeneous Frequencies.- A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip.- VI Power.- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture.- Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines.- HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic.- Compiler Controlled Speculationfor Power Aware ILP Extraction in Dataflow Architectures.- VII Cache Issues.- Revisiting Cache Block Superloading.- ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors.- In-Network Caching for Chip Multiprocessors.- VIII Parallel Embedded Applications.- Parallel LDPC Decoding on the Cell/B.E. Processor.- Parallel H.264 Decoding on an Embedded Multicore Processor.
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