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Flash Analog-to-Digital Converters (ADCs), targeting
optical communication standards, have been reported
in BiCMOS technology. CMOS implementation of such
designs faces two challenges. The first is to achieve
a high sampling speed, given the lower gain-bandwidth
of CMOS technology. The second challenge is to handle
the wide bandwidth of the input signal with certain
accuracy. Although the first problem can be relaxed
by using the time-interleaved architecture, the
second problem remains as a main obstacle to CMOS
implementation. Thus, this work analyzes the
bandwidth-accuracy product of flash ADCs, and
develops a circuit technique to improve the
bandwidth-accuracy product of flash ADCs in deep
submicron CMOS technologies. The performance
improvement that can be attained due to the proposed
circuit technique is demonstrated through the design
and implementation of a 6-bit 1.6-GS/s flash ADC in
0.13-Um CMOS technology.
This work is intended for researchers, graduate
students, and practicing engineers.
optical communication standards, have been reported
in BiCMOS technology. CMOS implementation of such
designs faces two challenges. The first is to achieve
a high sampling speed, given the lower gain-bandwidth
of CMOS technology. The second challenge is to handle
the wide bandwidth of the input signal with certain
accuracy. Although the first problem can be relaxed
by using the time-interleaved architecture, the
second problem remains as a main obstacle to CMOS
implementation. Thus, this work analyzes the
bandwidth-accuracy product of flash ADCs, and
develops a circuit technique to improve the
bandwidth-accuracy product of flash ADCs in deep
submicron CMOS technologies. The performance
improvement that can be attained due to the proposed
circuit technique is demonstrated through the design
and implementation of a 6-bit 1.6-GS/s flash ADC in
0.13-Um CMOS technology.
This work is intended for researchers, graduate
students, and practicing engineers.