Y. Lavanya, L. Bharathi, P Bhagyasree

HYBRID STORAGE CLASS MEMORIES SYSTEMS

A Secure Double Integrity Checking System Using Hybrid Storage Class Memories

• Broschiertes Buch

Produktbeschreibung

In this project the design of secure double integrity check system using hybrid storage class memories is implemented. Basically, the integrated chips are very complicated to increase the density of chip and decrease the size of chip. So to overcome this SCM array is implemented. Migration handler will handle the memories like non volatile memory and Dynamic random access memory. The memory controller bank will control the saved data following from NVM and DRAM manager. Now, this saved data will get mixed up by using double integrity controller. In this read and write operations are performed based on the W-SCM and R-SCM. At last the obtained data will be saved in memory cache bank. Hence from results it can observe that the hybrid SCM will reduce the delay in effective way.KEY WORDS: Random Access Memory (RAM), SCM (Storage Class Memories), Dynamic Random Access Memory (DRAM), Non Volatile Memory (NVM), W-SCM (Write Storage Class Memories) and R-SCM (Read Storage Class Memories).

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Produktdetails

• Verlag: LAP Lambert Academic Publishing
• Seitenzahl: 80
• Erscheinungstermin: 14. Juni 2021
• Englisch
• Abmessung: 220mm x 150mm x 5mm
• Gewicht: 137g
• ISBN-13: 9786203911084
• ISBN-10: 6203911089
• Artikelnr.: 62265517

Autorenporträt

La Sra. Y. Lavanya completó su B.Tech de Kuppam Engineering College, Kuppam en el año 2007 y completó M.Tech en el año 2013. En la actualidad, trabaja como profesora asociada en el Departamento de ECE, Ramachandra College of Engineering, Eluru. Tiene 12 años de excelente experiencia docente y ha publicado varios artículos de investigación