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The present research work is dedicated to quantify the impact of the geometry on memory performances in charge trap Flash memory devices. The main axes of research have been first to use a large set of electrical measurements, modeling and simulation made on planar devices. Then the acquainted knowledge has been applied to more complicated geometries and in particular Charge Trap Gate-All-Around devices (CT GAA), Charge Trap FinFET (CT FinFET) devices and CT Split-Gate devices. The two first are investigated for standalone application whereas the third one is investigated for embedded applications.