This textbook provides HDL-based examples, experiments, and projects that cover real industry needs such as design/coding rules and methodologies. It will help readers build a connection between the HDL code and hardware circuits.
This textbook provides HDL-based examples, experiments, and projects that cover real industry needs such as design/coding rules and methodologies. It will help readers build a connection between the HDL code and hardware circuits.
Dr. Xiaokun Yang currently serves as an Associate Professor at the College of Science and Engineering at the University of Houston Clear Lake, located in Houston, Texas. Additionally, since 2022, he has held the role of Affiliate Faculty at Lawrence Berkeley National Laboratory, situated in Berkeley, California. Dr. Yang earned his Ph.D. in the Department of Electrical and Computer Engineering at Florida International University (FIU) in the spring of 2016. He also brings extensive industry experience, having worked as ASIC Design and Verification Engineer at Advanced Micro Devices (AMD) and China Electronic Corporation (CEC) during 2007-2012. Dr. Yang's research interests center on specialized hardware design and acceleration for future high-performance computing, design automation for numerical hardware and machine learning, and advanced high-performance SoC architecture. As the first author or corresponding author, Dr. Yang has published more than 45 papers including 3 patents, more than 15 peer-review journals, and more than 30 prestigious international conferences. He has served as guest editor and journal reviewers including IEEE Transactions on Computer, IEEE Transactions on VLSI, IEEE Transactions on Education, ACM Transactions on Architecture and Code Optimization, and MDPI Micromachines, and numerous conference committees including ISQED and ISVLSI.
Inhaltsangabe
Chapter 1 Introduction to IC Design Chapter 2 IC Design Flow Chapter 3 Introduction to Verilog HDL Chapter 4 RTL Design with Verilog HDL Chapter 5 Design Simulation with Verilog HDL Chapter 6 Synthesis: Matching Verilog HDL with Basic Combinational and Sequential Circuits Chapter 7 FSM Design Chapter 8 FSM Datapath Design and Bus Communication Chapter 9 Numerical Hardware Design and Integration Chapter 10 Streaming and Iterative Design on Numerical Hardware Chapter 11 Timing Constraints and High Speed RTL Design Chapter 12 SoC Design and Integration
