Erik Larsson

Introduction to Advanced System-on-Chip Test Design and Optimization

• Gebundenes Buch

Produktbeschreibung

SOC test design and its optimization is the topic of Introduction to Advanced System-on-Chip Test Design and Optimization. It gives an introduction to testing, describes the problems related to SOC testing, discusses the modeling granularity and the implementation into EDA (electronic design automation) tools. The book is divided into three sections: i) test concepts, ii) SOC design for test, and iii) SOC test applications. The first part covers an introduction into test problems including faults, fault types, design-flow, design-for-test techniques such as scan-testing and Boundary Scan. The second part of the book discusses SOC related problems such as system modeling, test conflicts, power consumption, test access mechanism design, test scheduling and defect-oriented scheduling. Finally, the third part focuses on SOC applications, such as integrated test scheduling and TAM design, defect-oriented scheduling, and integrating test design with the core selection process.

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Produktdetails

• Frontiers in Electronic Testing 29
• Verlag: Springer / Springer Netherlands / Springer US
• Artikelnr. des Verlages: 978-1-4020-3207-3
• 2005
• Seitenzahl: 408
• Erscheinungstermin: 7. November 2005
• Englisch
• Abmessung: 241mm x 160mm x 27mm
• Gewicht: 792g
• ISBN-13: 9781402032073
• ISBN-10: 1402032072
• Artikelnr.: 14701086

Autorenporträt

Dr. Erik Larsson is an assistant professor at Linköpings University in Sweden, and he is an active member of the IEEE Testing and Circuits & Systems societies

Inhaltsangabe

Testing Concepts.- Design Flow.- Design for Test.- Boundary Scan.- SOC Design for Testability.- System Modeling.- Test Conflicts.- Test Power Dissipation.- Test Access Mechanism.- Test Scheduling.- SOC Test Applications.- A Reconfigurable Power-Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling.- An Integrated Framework for the Design and Optimization of SOC Test Solutions.- Efficient Test Solutions for Core-Based Designs.- Core Selection in the SOC Test Design-Flow.- Defect-Aware Test Scheduling.- An Integrated Technique for Test Vector Selection and Test Scheduling under ATE Memory Depth Constraint.