Sneh Saurabh

Introduction to VLSI Design Flow

• Broschiertes Buch

Produktbeschreibung

"Chip designing is a complex task that requires an in-depth understanding of VLSI design flow, skills to employ sophisticated design tools, and keeping pace with the bleeding-edge semiconductor technologies. This lucid textbook is focused on fulfilling these requirements for students, as well as a refresher for professionals in the industry. The book consists of four parts. The first part describes foundational concepts related to VLSI design flow and integrated circuits. It also gives an overview of the design, verification, and test methods employed in a typical VLSI design flow. The second part of the book describes the logic implementation and verification steps such as simulation, static timing analysis, and formal methods. It also explains the modelling of hardware using Verilog and logic synthesis; technology libraries; and timing constraints along with logic, power, and timing optimization techniques. The third part of the book describes the design for test (DFT) methods for digital circuits. The fourth and final part describes physical design methods and physical verification. All the physical design implementation steps such as floorplanning, placement, clock-tree synthesis, and routing are described in this part. Moreover, physical verification steps, such as parasitic extraction, design rule checks (DRCs), electrical rule checks (ERCs), layout versus schematic (LVS) checks, and post-silicon validation are explained. Illustrations and pictorial representations are used liberally to simplify the explanation. Additionally, activities are suggested at the end of relevant chapters to help readers gain a practical understanding of VLSI design flow. Review questions and problems are given at the end of each chapter to revise the concepts. Recent trends and references are listed at the end of each chapter for further reading"--

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Produktdetails

• Verlag: Greenwich Medical Media
• Seitenzahl: 800
• Erscheinungstermin: 15. Juni 2023
• Englisch
• Abmessung: 240mm x 180mm x 26mm
• Gewicht: 953g
• ISBN-13: 9781009200813
• ISBN-10: 100920081X
• Artikelnr.: 67327068

Autorenporträt

Sneh Saurabh is Associate Professor at the Department of Electronics and Communication Engineering at the Indraprastha Institute of Information Technology, New Delhi, India. He has rich experience in the semiconductor industry, having spent sixteen years working for industry leaders such as Cadence Design Systems, Synopsys India, and Magma Design Automation. His research interests include VLSI design and automation, nanoelectronics, and energy-efficient systems.

Inhaltsangabe

Part I. Overview of VLSI Design Flow: Chapter 1. Foundation
Chapter 2. Introduction to Integrated Circuits
Chapter 3. Pre-RTL Methodologies
Chapter 4. RTL to GDS Implementation Flow
Chapter 5. Verification Techniques
Chapter 6. Testing Techniques
Chapter 7. Post-GDS Processes
Part II. Logic Design: Chapter 8. Modeling Hardware using Verilog
Chapter 9. Simulation-based Verification
Chapter 10. RTL Synthesis
Chapter 11. Formal Verification, Chapter 12. Logic Optimization
Chapter 13. Technology Library
Chapter 14. Static Timing Analysis
Chapter 15. Constraints
Chapter 16. Technology Mapping
Chapter 17. Timing-driven Optimizations
Chapter 18. Power Analysis
Chapter 19. Power-driven Optimizations
Part III. Design for Testability (DFT): Chapter 20. Basics of DFT
Chapter 21. Scan Design
Chapter 22. Automatic Test Pattern Generation (ATPG)
Chapter 23. Built-in Self-test (BIST)
Part IV. Physical Design: Chapter 24. Basic Concepts for Physical Design
Chapter 25. Chip Planning
Chapter 26. Placement
Chapter 27. Clock Tree Synthesis (CTS)
Chapter 28. Routing
Chapter 29. Physical Verification and Signoff
Chapter 30. Post-silicon Validation.