Sneh Saurabh

Introduction to VLSI Design Flow

• Broschiertes Buch

Produktbeschreibung

This textbook focuses on developing practical skills in employing sophisticated design tools and proficiency in advanced VLSI design, covering the various stages of design implementation, verification, and testing. It will be a vital resource for students aspiring to join the semiconductor industry as well as a refresher for professionals.

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Produktdetails

• Verlag: Cambridge University Press
• Seitenzahl: 714
• Erscheinungstermin: 15. Juni 2023
• Englisch
• Abmessung: 246mm x 189mm x 38mm
• Gewicht: 1356g
• ISBN-13: 9781009200813
• ISBN-10: 100920081X
• Artikelnr.: 67327068

Autorenporträt

Sneh Saurabh is Associate Professor at the Department of Electronics and Communication Engineering at the Indraprastha Institute of Information Technology, New Delhi, India. He has rich experience in the semiconductor industry, having spent sixteen years working for industry leaders such as Cadence Design Systems, Synopsys India, and Magma Design Automation. His research interests include VLSI design and automation, nanoelectronics, and energy-efficient systems.

Inhaltsangabe

Part I. Overview of VLSI Design Flow: Chapter 1. Foundation
Chapter 2. Introduction to Integrated Circuits
Chapter 3. Pre-RTL Methodologies
Chapter 4. RTL to GDS Implementation Flow
Chapter 5. Verification Techniques
Chapter 6. Testing Techniques
Chapter 7. Post-GDS Processes
Part II. Logic Design: Chapter 8. Modeling Hardware using Verilog
Chapter 9. Simulation-based Verification
Chapter 10. RTL Synthesis
Chapter 11. Formal Verification, Chapter 12. Logic Optimization
Chapter 13. Technology Library
Chapter 14. Static Timing Analysis
Chapter 15. Constraints
Chapter 16. Technology Mapping
Chapter 17. Timing-driven Optimizations
Chapter 18. Power Analysis
Chapter 19. Power-driven Optimizations
Part III. Design for Testability (DFT): Chapter 20. Basics of DFT
Chapter 21. Scan Design
Chapter 22. Automatic Test Pattern Generation (ATPG)
Chapter 23. Built-in Self-test (BIST)
Part IV. Physical Design: Chapter 24. Basic Concepts for Physical Design
Chapter 25. Chip Planning
Chapter 26. Placement
Chapter 27. Clock Tree Synthesis (CTS)
Chapter 28. Routing
Chapter 29. Physical Verification and Signoff
Chapter 30. Post-silicon Validation.